[PATCH v1 0/4] MediaTek CIRQ: new register layout and schema

[PATCH v1 0/4] MediaTek CIRQ: new register layout and schema

[AngeloGioacchino Del Regno]

On newer SoCs (like MT8192/95 and also other non-chromebook chips), the
MediaTek CIRQ controller has a new register layout: this series adds
some more flexibility to the irq-mtk-cirq driver, allowing to select
the register layout based on a SoC-specific compatible.

While at it, I've also performed a schema conversion .. because why not.

This was tested on MT8173 Elm, MT8192 Asurada, MT8195 Tomato (where
the latter require devicetree work to actually make use of the CIRQ,
not included in this series).

AngeloGioacchino Del Regno (4):
  dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema
  dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192
  irqchip: irq-mtk-cirq: Move register offsets to const array
  irqchip: irq-mtk-cirq: Add support for System CIRQ on MT8192

 .../interrupt-controller/mediatek,cirq.txt    | 33 --------
 .../mediatek,mtk-cirq.yaml                    | 71 ++++++++++++++++
 drivers/irqchip/irq-mtk-cirq.c                | 81 ++++++++++++++-----
 3 files changed, 134 insertions(+), 51 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml

-- 
2.38.1


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[PATCH v1 1/4] dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema

[AngeloGioacchino Del Regno]

Migrate mediatek,cirq.txt to dt schema as mediatek,mtk-cirq.yaml.
While at it, I've also fixed some typos that were present in the
original txt binding, as it was suggesting that the compatible
string would have "mediatek,cirq" as compatible but, in reality,
that's supposed to be "mediatek,mtk-cirq" instead.

Little rewording on property descriptions also happened for
them to be more concise.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../interrupt-controller/mediatek,cirq.txt    | 33 ---------
 .../mediatek,mtk-cirq.yaml                    | 70 +++++++++++++++++++
 2 files changed, 70 insertions(+), 33 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
deleted file mode 100644
index 5865f4f2c69d..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Mediatek 27xx cirq
-
-In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to
-work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
-The external interrupts (outside MCUSYS) will feed through CIRQ and connect
-to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
-interrupts and generate a pulse signal to parent interrupt controller when
-flush command is executed. With CIRQ, MCUSYS can be completely turned off
-to improve the system power consumption without losing interrupts.
-
-Required properties:
-- compatible: should be one of
-  - "mediatek,mt2701-cirq" for mt2701 CIRQ
-  - "mediatek,mt8135-cirq" for mt8135 CIRQ
-  - "mediatek,mt8173-cirq" for mt8173 CIRQ
-  and "mediatek,cirq" as a fallback.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
-- reg: Physical base address of the cirq registers and length of memory
-  mapped region.
-- mediatek,ext-irq-range: Identifies external irq number range in different
-  SOCs.
-
-Example:
-	cirq: interrupt-controller@10204000 {
-		compatible = "mediatek,mt2701-cirq",
-			     "mediatek,mtk-cirq";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&sysirq>;
-		reg = <0 0x10204000 0 0x400>;
-		mediatek,ext-irq-start = <32 200>;
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
new file mode 100644
index 000000000000..21e709169907
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Interrupt Controller
+
+maintainers:
+  - Youlin Pei <youlin.pei@mediatek.com>
+
+description:
+  In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to
+  work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
+  The external interrupts (outside MCUSYS) will feed through CIRQ and connect
+  to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
+  interrupts and generate a pulse signal to parent interrupt controller when
+  flush command is executed. With CIRQ, MCUSYS can be completely turned off
+  to improve the system power consumption without losing interrupts.
+
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt2701-cirq
+          - mediatek,mt8135-cirq
+          - mediatek,mt8173-cirq
+      - const: mediatek,mtk-cirq
+
+  reg:
+    maxItems: 1
+    description: Address and size of the CIRQ registers
+
+  '#interrupt-cells':
+    const: 3
+
+  interrupt-controller: true
+
+  mediatek,ext-irq-range:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    maxItems: 1
+    items:
+      items:
+        - description: First CIRQ interrupt
+        - description: Last CIRQ interrupt
+    description:
+      Identifies the range of external interrupts in different SoCs
+
+required:
+  - compatible
+  - reg
+  - '#interrupt-cells'
+  - interrupt-controller
+  - mediatek,ext-irq-range
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    cirq: interrupt-controller@10204000 {
+        compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq";
+        reg = <0x10204000 0x400>;
+        #interrupt-cells = <3>;
+        interrupt-controller;
+        interrupt-parent = <&sysirq>;
+        mediatek,ext-irq-range = <32 200>;
+    };
-- 
2.38.1


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Re: [PATCH v1 1/4] dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema

[Krzysztof Kozlowski]

On 18/11/2022 11:06, AngeloGioacchino Del Regno wrote:
> Migrate mediatek,cirq.txt to dt schema as mediatek,mtk-cirq.yaml.
> While at it, I've also fixed some typos that were present in the
> original txt binding, as it was suggesting that the compatible
> string would have "mediatek,cirq" as compatible but, in reality,
> that's supposed to be "mediatek,mtk-cirq" instead.
> 
> Little rewording on property descriptions also happened for
> them to be more concise.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../interrupt-controller/mediatek,cirq.txt    | 33 ---------
>  .../mediatek,mtk-cirq.yaml                    | 70 +++++++++++++++++++
>  2 files changed, 70 insertions(+), 33 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
> deleted file mode 100644
> index 5865f4f2c69d..000000000000
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -* Mediatek 27xx cirq
> -
> -In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to
> -work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
> -The external interrupts (outside MCUSYS) will feed through CIRQ and connect
> -to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
> -interrupts and generate a pulse signal to parent interrupt controller when
> -flush command is executed. With CIRQ, MCUSYS can be completely turned off
> -to improve the system power consumption without losing interrupts.
> -
> -Required properties:
> -- compatible: should be one of
> -  - "mediatek,mt2701-cirq" for mt2701 CIRQ
> -  - "mediatek,mt8135-cirq" for mt8135 CIRQ
> -  - "mediatek,mt8173-cirq" for mt8173 CIRQ
> -  and "mediatek,cirq" as a fallback.
> -- interrupt-controller : Identifies the node as an interrupt controller.
> -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
> -- reg: Physical base address of the cirq registers and length of memory
> -  mapped region.
> -- mediatek,ext-irq-range: Identifies external irq number range in different
> -  SOCs.
> -
> -Example:
> -	cirq: interrupt-controller@10204000 {
> -		compatible = "mediatek,mt2701-cirq",
> -			     "mediatek,mtk-cirq";
> -		interrupt-controller;
> -		#interrupt-cells = <3>;
> -		interrupt-parent = <&sysirq>;
> -		reg = <0 0x10204000 0 0x400>;
> -		mediatek,ext-irq-start = <32 200>;
> -	};
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
> new file mode 100644
> index 000000000000..21e709169907
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Interrupt Controller
> +
> +maintainers:
> +  - Youlin Pei <youlin.pei@mediatek.com>
> +
> +description:
> +  In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to
> +  work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
> +  The external interrupts (outside MCUSYS) will feed through CIRQ and connect
> +  to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
> +  interrupts and generate a pulse signal to parent interrupt controller when
> +  flush command is executed. With CIRQ, MCUSYS can be completely turned off
> +  to improve the system power consumption without losing interrupts.
> +
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt2701-cirq
> +          - mediatek,mt8135-cirq
> +          - mediatek,mt8173-cirq
> +      - const: mediatek,mtk-cirq
> +
> +  reg:
> +    maxItems: 1
> +    description: Address and size of the CIRQ registers

Drop description, it's obvious.

> +
> +  '#interrupt-cells':
> +    const: 3
> +
> +  interrupt-controller: true
> +
> +  mediatek,ext-irq-range:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    maxItems: 1

This points it's array..

> +    items:
> +      items:

But this it's matrix.

> +        - description: First CIRQ interrupt
> +        - description: Last CIRQ interrupt

I guess it you should be just array with only one "items:" keyword.

> +    description:
> +      Identifies the range of external interrupts in different SoCs
> +

Best regards,
Krzysztof


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[PATCH v1 2/4] dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192

[AngeloGioacchino Del Regno]

Add compatible to support the SYS_CIRQ controller found on MT8192.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../bindings/interrupt-controller/mediatek,mtk-cirq.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
index 21e709169907..e0d483d3b1fb 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml
@@ -26,6 +26,7 @@ properties:
           - mediatek,mt2701-cirq
           - mediatek,mt8135-cirq
           - mediatek,mt8173-cirq
+          - mediatek,mt8192-cirq
       - const: mediatek,mtk-cirq
 
   reg:
-- 
2.38.1


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Re: [PATCH v1 2/4] dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192

[Krzysztof Kozlowski]

On 18/11/2022 11:06, AngeloGioacchino Del Regno wrote:
> Add compatible to support the SYS_CIRQ controller found on MT8192.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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[PATCH v1 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array

[AngeloGioacchino Del Regno]

In preparation to add support for new SoCs having different register
offsets, add an enumeration that documents registers and move the
register offsets definitions to a u32 array.

Of course, every usage of the definitions was changed to use the
newly introduced register offsets array.

This change brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/irqchip/irq-mtk-cirq.c | 62 ++++++++++++++++++++++++----------
 1 file changed, 44 insertions(+), 18 deletions(-)

diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
index 9bca0918078e..affbc0f48550 100644
--- a/drivers/irqchip/irq-mtk-cirq.c
+++ b/drivers/irqchip/irq-mtk-cirq.c
@@ -15,14 +15,30 @@
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 
-#define CIRQ_ACK	0x40
-#define CIRQ_MASK_SET	0xc0
-#define CIRQ_MASK_CLR	0x100
-#define CIRQ_SENS_SET	0x180
-#define CIRQ_SENS_CLR	0x1c0
-#define CIRQ_POL_SET	0x240
-#define CIRQ_POL_CLR	0x280
-#define CIRQ_CONTROL	0x300
+enum mtk_cirq_reg_index {
+	CIRQ_STA = 0,
+	CIRQ_ACK,
+	CIRQ_MASK_SET,
+	CIRQ_MASK_CLR,
+	CIRQ_SENS_SET,
+	CIRQ_SENS_CLR,
+	CIRQ_POL_SET,
+	CIRQ_POL_CLR,
+	CIRQ_CONTROL,
+	CIRQ_MAX
+};
+
+static const u32 mtk_cirq_regs_v1[] = {
+	[CIRQ_STA]	= 0x0,
+	[CIRQ_ACK]	= 0x40,
+	[CIRQ_MASK_SET]	= 0xc0,
+	[CIRQ_MASK_CLR]	= 0x100,
+	[CIRQ_SENS_SET]	= 0x180,
+	[CIRQ_SENS_CLR]	= 0x1c0,
+	[CIRQ_POL_SET]	= 0x240,
+	[CIRQ_POL_CLR]	= 0x280,
+	[CIRQ_CONTROL]	= 0x300,
+};
 
 #define CIRQ_EN	0x1
 #define CIRQ_EDGE	0x2
@@ -32,18 +48,20 @@ struct mtk_cirq_chip_data {
 	void __iomem *base;
 	unsigned int ext_irq_start;
 	unsigned int ext_irq_end;
+	const u32 *regs;
 	struct irq_domain *domain;
 };
 
 static struct mtk_cirq_chip_data *cirq_data;
 
-static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
+static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_reg_index idx)
 {
 	struct mtk_cirq_chip_data *chip_data = data->chip_data;
 	unsigned int cirq_num = data->hwirq;
 	u32 mask = 1 << (cirq_num % 32);
+	u32 reg = chip_data->regs[idx] + (cirq_num / 32) * 4;
 
-	writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
+	writel_relaxed(mask, chip_data->base + reg);
 }
 
 static void mtk_cirq_mask(struct irq_data *data)
@@ -160,7 +178,7 @@ static const struct irq_domain_ops cirq_domain_ops = {
 #ifdef CONFIG_PM_SLEEP
 static int mtk_cirq_suspend(void)
 {
-	u32 value, mask;
+	u32 value, mask, reg;
 	unsigned int irq, hwirq_num;
 	bool pending, masked;
 	int i, pendret, maskret;
@@ -200,31 +218,34 @@ static int mtk_cirq_suspend(void)
 				continue;
 		}
 
+		reg = cirq_data->regs[CIRQ_ACK] + (i / 32) * 4;
 		mask = 1 << (i % 32);
-		writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
+		writel_relaxed(mask, cirq_data->base + reg);
 	}
 
 	/* set edge_only mode, record edge-triggerd interrupts */
 	/* enable cirq */
-	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
+	reg = cirq_data->regs[CIRQ_CONTROL];
+	value = readl_relaxed(cirq_data->base + reg);
 	value |= (CIRQ_EDGE | CIRQ_EN);
-	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
+	writel_relaxed(value, cirq_data->base + reg);
 
 	return 0;
 }
 
 static void mtk_cirq_resume(void)
 {
+	u32 reg = cirq_data->regs[CIRQ_CONTROL];
 	u32 value;
 
 	/* flush recorded interrupts, will send signals to parent controller */
-	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
-	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
+	value = readl_relaxed(cirq_data->base + reg);
+	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + reg);
 
 	/* disable cirq */
-	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
+	value = readl_relaxed(cirq_data->base + reg);
 	value &= ~(CIRQ_EDGE | CIRQ_EN);
-	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
+	writel_relaxed(value, cirq_data->base + reg);
 }
 
 static struct syscore_ops mtk_cirq_syscore_ops = {
@@ -240,6 +261,9 @@ static void mtk_cirq_syscore_init(void)
 static inline void mtk_cirq_syscore_init(void) {}
 #endif
 
+static const struct of_device_id mtk_cirq_of_match[] = {
+	{ .compatible = "mediatek,
+
 static int __init mtk_cirq_of_init(struct device_node *node,
 				   struct device_node *parent)
 {
@@ -274,6 +298,8 @@ static int __init mtk_cirq_of_init(struct device_node *node,
 	if (ret)
 		goto out_unmap;
 
+	cirq_data->regs = mtk_cirq_regs_v1;
+
 	irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
 	domain = irq_domain_add_hierarchy(domain_parent, 0,
 					  irq_num, node,
-- 
2.38.1


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Re: [PATCH v1 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array

[Marc Zyngier]

On Fri, 18 Nov 2022 10:06:38 +0000,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:
> 
> In preparation to add support for new SoCs having different register
> offsets, add an enumeration that documents registers and move the
> register offsets definitions to a u32 array.
> 
> Of course, every usage of the definitions was changed to use the
> newly introduced register offsets array.
> 
> This change brings no functional changes.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/irqchip/irq-mtk-cirq.c | 62 ++++++++++++++++++++++++----------
>  1 file changed, 44 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
> index 9bca0918078e..affbc0f48550 100644
> --- a/drivers/irqchip/irq-mtk-cirq.c
> +++ b/drivers/irqchip/irq-mtk-cirq.c
> @@ -15,14 +15,30 @@
>  #include <linux/slab.h>
>  #include <linux/syscore_ops.h>
>  
> -#define CIRQ_ACK	0x40
> -#define CIRQ_MASK_SET	0xc0
> -#define CIRQ_MASK_CLR	0x100
> -#define CIRQ_SENS_SET	0x180
> -#define CIRQ_SENS_CLR	0x1c0
> -#define CIRQ_POL_SET	0x240
> -#define CIRQ_POL_CLR	0x280
> -#define CIRQ_CONTROL	0x300
> +enum mtk_cirq_reg_index {
> +	CIRQ_STA = 0,

Enums starting from 0 are the default.

> +	CIRQ_ACK,
> +	CIRQ_MASK_SET,
> +	CIRQ_MASK_CLR,
> +	CIRQ_SENS_SET,
> +	CIRQ_SENS_CLR,
> +	CIRQ_POL_SET,
> +	CIRQ_POL_CLR,
> +	CIRQ_CONTROL,
> +	CIRQ_MAX

What's the use of this last constant?

> +};
> +
> +static const u32 mtk_cirq_regs_v1[] = {
> +	[CIRQ_STA]	= 0x0,
> +	[CIRQ_ACK]	= 0x40,
> +	[CIRQ_MASK_SET]	= 0xc0,
> +	[CIRQ_MASK_CLR]	= 0x100,
> +	[CIRQ_SENS_SET]	= 0x180,
> +	[CIRQ_SENS_CLR]	= 0x1c0,
> +	[CIRQ_POL_SET]	= 0x240,
> +	[CIRQ_POL_CLR]	= 0x280,
> +	[CIRQ_CONTROL]	= 0x300,
> +};
>  
>  #define CIRQ_EN	0x1
>  #define CIRQ_EDGE	0x2
> @@ -32,18 +48,20 @@ struct mtk_cirq_chip_data {
>  	void __iomem *base;
>  	unsigned int ext_irq_start;
>  	unsigned int ext_irq_end;
> +	const u32 *regs;

This is an array of *offsets*, not registers. Please name it accordingly.

>  	struct irq_domain *domain;
>  };
>  
>  static struct mtk_cirq_chip_data *cirq_data;
>  
> -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
> +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_reg_index idx)
>  {
>  	struct mtk_cirq_chip_data *chip_data = data->chip_data;
>  	unsigned int cirq_num = data->hwirq;
>  	u32 mask = 1 << (cirq_num % 32);
> +	u32 reg = chip_data->regs[idx] + (cirq_num / 32) * 4;

Please provide an accessor that takes chip_data and an index, and
returns an address.

>  
> -	writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
> +	writel_relaxed(mask, chip_data->base + reg);
>  }
>  
>  static void mtk_cirq_mask(struct irq_data *data)
> @@ -160,7 +178,7 @@ static const struct irq_domain_ops cirq_domain_ops = {
>  #ifdef CONFIG_PM_SLEEP
>  static int mtk_cirq_suspend(void)
>  {
> -	u32 value, mask;
> +	u32 value, mask, reg;
>  	unsigned int irq, hwirq_num;
>  	bool pending, masked;
>  	int i, pendret, maskret;
> @@ -200,31 +218,34 @@ static int mtk_cirq_suspend(void)
>  				continue;
>  		}
>  
> +		reg = cirq_data->regs[CIRQ_ACK] + (i / 32) * 4;
>  		mask = 1 << (i % 32);
> -		writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
> +		writel_relaxed(mask, cirq_data->base + reg);
>  	}
>  
>  	/* set edge_only mode, record edge-triggerd interrupts */
>  	/* enable cirq */
> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> +	reg = cirq_data->regs[CIRQ_CONTROL];
> +	value = readl_relaxed(cirq_data->base + reg);
>  	value |= (CIRQ_EDGE | CIRQ_EN);
> -	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
> +	writel_relaxed(value, cirq_data->base + reg);
>  
>  	return 0;
>  }
>  
>  static void mtk_cirq_resume(void)
>  {
> +	u32 reg = cirq_data->regs[CIRQ_CONTROL];
>  	u32 value;
>  
>  	/* flush recorded interrupts, will send signals to parent controller */
> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> -	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
> +	value = readl_relaxed(cirq_data->base + reg);
> +	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + reg);
>  
>  	/* disable cirq */
> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
> +	value = readl_relaxed(cirq_data->base + reg);
>  	value &= ~(CIRQ_EDGE | CIRQ_EN);
> -	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
> +	writel_relaxed(value, cirq_data->base + reg);
>  }
>  
>  static struct syscore_ops mtk_cirq_syscore_ops = {
> @@ -240,6 +261,9 @@ static void mtk_cirq_syscore_init(void)
>  static inline void mtk_cirq_syscore_init(void) {}
>  #endif
>  
> +static const struct of_device_id mtk_cirq_of_match[] = {
> +	{ .compatible = "mediatek,
> +

I can tell by this hunk the quality of testing this patch has
received.

>  static int __init mtk_cirq_of_init(struct device_node *node,
>  				   struct device_node *parent)
>  {
> @@ -274,6 +298,8 @@ static int __init mtk_cirq_of_init(struct device_node *node,
>  	if (ret)
>  		goto out_unmap;
>  
> +	cirq_data->regs = mtk_cirq_regs_v1;

Why isn't this obtained from the matching array?

> +
>  	irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
>  	domain = irq_domain_add_hierarchy(domain_parent, 0,
>  					  irq_num, node,

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v1 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array

[AngeloGioacchino Del Regno]

Il 22/11/22 14:03, Marc Zyngier ha scritto:
> On Fri, 18 Nov 2022 10:06:38 +0000,
> AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:
>>
>> In preparation to add support for new SoCs having different register
>> offsets, add an enumeration that documents registers and move the
>> register offsets definitions to a u32 array.
>>
>> Of course, every usage of the definitions was changed to use the
>> newly introduced register offsets array.
>>
>> This change brings no functional changes.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/irqchip/irq-mtk-cirq.c | 62 ++++++++++++++++++++++++----------
>>   1 file changed, 44 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
>> index 9bca0918078e..affbc0f48550 100644
>> --- a/drivers/irqchip/irq-mtk-cirq.c
>> +++ b/drivers/irqchip/irq-mtk-cirq.c
>> @@ -15,14 +15,30 @@
>>   #include <linux/slab.h>
>>   #include <linux/syscore_ops.h>
>>   
>> -#define CIRQ_ACK	0x40
>> -#define CIRQ_MASK_SET	0xc0
>> -#define CIRQ_MASK_CLR	0x100
>> -#define CIRQ_SENS_SET	0x180
>> -#define CIRQ_SENS_CLR	0x1c0
>> -#define CIRQ_POL_SET	0x240
>> -#define CIRQ_POL_CLR	0x280
>> -#define CIRQ_CONTROL	0x300
>> +enum mtk_cirq_reg_index {
>> +	CIRQ_STA = 0,
> 
> Enums starting from 0 are the default.
> 
>> +	CIRQ_ACK,
>> +	CIRQ_MASK_SET,
>> +	CIRQ_MASK_CLR,
>> +	CIRQ_SENS_SET,
>> +	CIRQ_SENS_CLR,
>> +	CIRQ_POL_SET,
>> +	CIRQ_POL_CLR,
>> +	CIRQ_CONTROL,
>> +	CIRQ_MAX
> 
> What's the use of this last constant?
> 

None, was commodity for loops - will remove, thanks.

>> +};
>> +
>> +static const u32 mtk_cirq_regs_v1[] = {
>> +	[CIRQ_STA]	= 0x0,
>> +	[CIRQ_ACK]	= 0x40,
>> +	[CIRQ_MASK_SET]	= 0xc0,
>> +	[CIRQ_MASK_CLR]	= 0x100,
>> +	[CIRQ_SENS_SET]	= 0x180,
>> +	[CIRQ_SENS_CLR]	= 0x1c0,
>> +	[CIRQ_POL_SET]	= 0x240,
>> +	[CIRQ_POL_CLR]	= 0x280,
>> +	[CIRQ_CONTROL]	= 0x300,
>> +};
>>   
>>   #define CIRQ_EN	0x1
>>   #define CIRQ_EDGE	0x2
>> @@ -32,18 +48,20 @@ struct mtk_cirq_chip_data {
>>   	void __iomem *base;
>>   	unsigned int ext_irq_start;
>>   	unsigned int ext_irq_end;
>> +	const u32 *regs;
> 
> This is an array of *offsets*, not registers. Please name it accordingly.
> 

Will do

>>   	struct irq_domain *domain;
>>   };
>>   
>>   static struct mtk_cirq_chip_data *cirq_data;
>>   
>> -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
>> +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_reg_index idx)
>>   {
>>   	struct mtk_cirq_chip_data *chip_data = data->chip_data;
>>   	unsigned int cirq_num = data->hwirq;
>>   	u32 mask = 1 << (cirq_num % 32);
>> +	u32 reg = chip_data->regs[idx] + (cirq_num / 32) * 4;
> 
> Please provide an accessor that takes chip_data and an index, and
> returns an address.
> 

Ack.

>>   
>> -	writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
>> +	writel_relaxed(mask, chip_data->base + reg);
>>   }
>>   
>>   static void mtk_cirq_mask(struct irq_data *data)
>> @@ -160,7 +178,7 @@ static const struct irq_domain_ops cirq_domain_ops = {
>>   #ifdef CONFIG_PM_SLEEP
>>   static int mtk_cirq_suspend(void)
>>   {
>> -	u32 value, mask;
>> +	u32 value, mask, reg;
>>   	unsigned int irq, hwirq_num;
>>   	bool pending, masked;
>>   	int i, pendret, maskret;
>> @@ -200,31 +218,34 @@ static int mtk_cirq_suspend(void)
>>   				continue;
>>   		}
>>   
>> +		reg = cirq_data->regs[CIRQ_ACK] + (i / 32) * 4;
>>   		mask = 1 << (i % 32);
>> -		writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
>> +		writel_relaxed(mask, cirq_data->base + reg);
>>   	}
>>   
>>   	/* set edge_only mode, record edge-triggerd interrupts */
>>   	/* enable cirq */
>> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
>> +	reg = cirq_data->regs[CIRQ_CONTROL];
>> +	value = readl_relaxed(cirq_data->base + reg);
>>   	value |= (CIRQ_EDGE | CIRQ_EN);
>> -	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
>> +	writel_relaxed(value, cirq_data->base + reg);
>>   
>>   	return 0;
>>   }
>>   
>>   static void mtk_cirq_resume(void)
>>   {
>> +	u32 reg = cirq_data->regs[CIRQ_CONTROL];
>>   	u32 value;
>>   
>>   	/* flush recorded interrupts, will send signals to parent controller */
>> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
>> -	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
>> +	value = readl_relaxed(cirq_data->base + reg);
>> +	writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + reg);
>>   
>>   	/* disable cirq */
>> -	value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
>> +	value = readl_relaxed(cirq_data->base + reg);
>>   	value &= ~(CIRQ_EDGE | CIRQ_EN);
>> -	writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
>> +	writel_relaxed(value, cirq_data->base + reg);
>>   }
>>   
>>   static struct syscore_ops mtk_cirq_syscore_ops = {
>> @@ -240,6 +261,9 @@ static void mtk_cirq_syscore_init(void)
>>   static inline void mtk_cirq_syscore_init(void) {}
>>   #endif
>>   
>> +static const struct of_device_id mtk_cirq_of_match[] = {
>> +	{ .compatible = "mediatek,
>> +
> 
> I can tell by this hunk the quality of testing this patch has
> received.
> 

Actually, the testing was performed on multiple SoCs.

As for why this is there, check below...

>>   static int __init mtk_cirq_of_init(struct device_node *node,
>>   				   struct device_node *parent)
>>   {
>> @@ -274,6 +298,8 @@ static int __init mtk_cirq_of_init(struct device_node *node,
>>   	if (ret)
>>   		goto out_unmap;
>>   
>> +	cirq_data->regs = mtk_cirq_regs_v1;
> 
> Why isn't this obtained from the matching array?
> 

.... I'm truly sorry for what happened, I've just checked - the right patchset
was in a different folder and I've somehow sent the wrong one.

Sorry again - will send a v2 ASAP.

Best regards,
Angelo

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[PATCH v1 4/4] irqchip: irq-mtk-cirq: Add support for System CIRQ on MT8192

[AngeloGioacchino Del Regno]

On some SoCs the System CIRQ register layout is slightly different,
as there are more registers per function and in some cases other
differences later in the layout: this is seen on at least MT8192,
but it's also valid for some other "contemporary" SoCs both for
Chromebooks and for smartphones.

Add the new "v2" register layout and use it if the compatible
"mediatek,mt8192-cirq" is found; to retain compatibility with
older devicetrees and/or with SoCs that don't need any register
layout variation, if no "special" compatible is found, we use
the "v1" register layout by default.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/irqchip/irq-mtk-cirq.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c
index affbc0f48550..8d6b3d9c40cf 100644
--- a/drivers/irqchip/irq-mtk-cirq.c
+++ b/drivers/irqchip/irq-mtk-cirq.c
@@ -40,6 +40,18 @@ static const u32 mtk_cirq_regs_v1[] = {
 	[CIRQ_CONTROL]	= 0x300,
 };
 
+static const u32 mtk_cirq_regs_v2[] = {
+	[CIRQ_STA]	= 0x0,
+	[CIRQ_ACK]	= 0x80,
+	[CIRQ_MASK_SET]	= 0x180,
+	[CIRQ_MASK_CLR]	= 0x200,
+	[CIRQ_SENS_SET]	= 0x300,
+	[CIRQ_SENS_CLR]	= 0x380,
+	[CIRQ_POL_SET]	= 0x480,
+	[CIRQ_POL_CLR]	= 0x500,
+	[CIRQ_CONTROL]	= 0x600,
+};
+
 #define CIRQ_EN	0x1
 #define CIRQ_EDGE	0x2
 #define CIRQ_FLUSH	0x4
@@ -262,12 +274,15 @@ static inline void mtk_cirq_syscore_init(void) {}
 #endif
 
 static const struct of_device_id mtk_cirq_of_match[] = {
-	{ .compatible = "mediatek,
+	{ .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regs_v2 },
+	{ /* sentinel */ }
+};
 
 static int __init mtk_cirq_of_init(struct device_node *node,
 				   struct device_node *parent)
 {
 	struct irq_domain *domain, *domain_parent;
+	const struct of_device_id *match;
 	unsigned int irq_num;
 	int ret;
 
@@ -298,7 +313,11 @@ static int __init mtk_cirq_of_init(struct device_node *node,
 	if (ret)
 		goto out_unmap;
 
-	cirq_data->regs = mtk_cirq_regs_v1;
+	match = of_match_node(mtk_cirq_of_match, node);
+	if (match)
+		cirq_data->regs = match->data;
+	else
+		cirq_data->regs = mtk_cirq_regs_v1;
 
 	irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
 	domain = irq_domain_add_hierarchy(domain_parent, 0,
-- 
2.38.1


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