From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7009FCD98F2 for ; Tue, 23 Jun 2026 17:02:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aBU6pCnOCTlrKDDQo5rEGB3OdGcEdLqLcPo64Ew0+ZM=; b=ZAkMgtGisnf+zwvL6zX+6GiCEF DnUVNQ7RORI+lebm2r7JufWiwRumzYRicnw47/YzkpllPLSIo598MOm7hCDrNbjUwVcbnnFdUaPBQ 7NFmHf5hrU7qGgYxXrr7k3wJwQtysa9D6eydQSpQdyvVkWIDWn9uy+Q6BrDsjOQq286Gdvj4zp1JQ /PAqtfKenIaKIWxoJZz134b1hKCc04/nthKf2hhnsxNRgkLTn3JkiWOmohdHqQ0/U1pBDz3UC/blC 0b1cGJdBG9Onj5oJlvvmSpzQtvOdR05QZ5IdagagmxMqsP7iISDJUxz2Z+TKQBFuH5FiKUOv4kei4 jl6oJvYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wc4WM-00000006flC-0rSF; Tue, 23 Jun 2026 17:02:46 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wc4WK-00000006fkv-2xdi for linux-arm-kernel@lists.infradead.org; Tue, 23 Jun 2026 17:02:44 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id BA12960018; Tue, 23 Jun 2026 17:02:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6E8201F000E9; Tue, 23 Jun 2026 17:02:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1782234163; bh=aBU6pCnOCTlrKDDQo5rEGB3OdGcEdLqLcPo64Ew0+ZM=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=LlI9FAR3V2CgWMRUYHx/Pp9RazmkuGtTnZYI9Uvf8uIWjc4H9Wo+izN90npoglUMQ yQt6RhXDyYsdwpNlP6XSA4s/hzUYUZ6pbIix9ox+bYTbj4PhkFq8rNJyaBPzdBl1ky k00ceYbUFinHQ3/PJsMyWmjGF4jlqJcpAjCjnlpUqejzM3SgcnG5w+IcVc6EDcZfA/ zYwLkikMu+Urz8T5fVKecSXBDE9L9leseBpv74ZXGgEW3gQrleJQosDm1qb/3ba3UH ZdbAetHjTGTU38VLT5TqtbA90HD+VHu4h5wceBO9OHldpMimKX7hepTQE3DZilrI4V UoNo7Fk98M9PQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wc4WH-0000000FMe4-12PY; Tue, 23 Jun 2026 17:02:41 +0000 Date: Tue, 23 Jun 2026 18:02:40 +0100 Message-ID: <86qzlxqjf3.wl-maz@kernel.org> From: Marc Zyngier To: Bradley Morgan Cc: Oliver Upton , kvmarm@lists.linux.dev, Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Quentin Perret , Vincent Donnefort , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2 1/2] KVM: arm64: skip pKVM cache flushes for non cacheable mappings In-Reply-To: <20260623163756.4591-1-include@grrlz.net> References: <20260623160339.15143-1-include@grrlz.net> <20260623163756.4591-1-include@grrlz.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: include@grrlz.net, oupton@kernel.org, kvmarm@lists.linux.dev, tabba@google.com, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, qperret@google.com, vdonnefort@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Bradley, Just a few things to keep in mind for your next contributions: - If you are sending more than a single patch, add a cover letter. - Don't send a v2 in reply to a v1. It messes the threading we are relying on, and makes it hard to ignore replies to an older version. Always send new series standalone. - Don't immediately send a V2, even if (especially if!) a bot is pestering you. 34 minutes between versions is way too short (at least a few days is the norm). On Tue, 23 Jun 2026 17:37:55 +0100, Bradley Morgan wrote: > > pKVM keeps its own mapping list for stage 2 operations. Its flush path > uses that list directly, so it lost the PTE attribute check done by the > generic stage 2 walker. > > Record whether a mapping is cacheable and skip cache maintenance for > mappings that are not cacheable. > > Fixes: e912efed485a ("KVM: arm64: Introduce the EL1 pKVM MMU") > Cc: stable@vger.kernel.org What device memory gets mapped in an upstream pKVM guest that would require a backport to stable? > Signed-off-by: Bradley Morgan > --- > Changes in v2: > - Add patch 2 for the pKVM permission fault mapping cache bug. This is the sort of information that goes in the cover letter. > > arch/arm64/include/asm/kvm_pkvm.h | 1 + > arch/arm64/kvm/pkvm.c | 8 +++++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm_pkvm.h > index 74fedd9c5ff0..d9dd8239910d 100644 > --- a/arch/arm64/include/asm/kvm_pkvm.h > +++ b/arch/arm64/include/asm/kvm_pkvm.h > @@ -196,6 +196,7 @@ struct pkvm_mapping { > u64 gfn; > u64 pfn; > u64 nr_pages; > + bool cacheable; Errr, no. That's a terrible idea. This thing is already big enough, let's not add a bool right in the middle (use pahole to find out why this is bad). Given that nr_pages is for a range, and that the minimum page size uses 12 bits, the largest number of pages you can have here is 56-12=48 bit wide. That's another 16 bits worth of flags you can use. Thanks, M. -- Without deviation from the norm, progress is not possible.