From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2238CCD98F2 for ; Wed, 17 Jun 2026 17:32:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/SQnDjjaa+ApH6wWe2aDhouAw1YQxs5X6sfF4wLVHvU=; b=fhny/bOhY3U0w3CvXI92RnMs7r WGWOVGCJ2acF2Dl+8z2Y/RqvDN+hA1+YJ3wx3qgbOOoAaXyeq6MyertnUiOuWom3+KYKq4tQDC48e Ht8CtOx29MAEvO86czcdPaV5Yf5f1Av+WWkAhSqm+W6d/KlKRHR2G7nXbenf2bNGjoM74rswXpFRr No04WaJYeLsy4IbLxntgM1s0PzUr332dEzotxnfSZPDEs67z7qeGGBMs/Lcj+OvwKBF1zcYv9GxY5 Hqom4Qysj91+THEO12zHesNdBEAwCeq5eUNiFTG2sN0fIVO7p4z02IVOCcX3RRrwg4asoLzVkAsRR njY+URxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZu85-000000007BU-474A; Wed, 17 Jun 2026 17:32:45 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZu84-000000007BI-1t7G for linux-arm-kernel@lists.infradead.org; Wed, 17 Jun 2026 17:32:44 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 72A736001D; Wed, 17 Jun 2026 17:32:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F34DB1F000E9; Wed, 17 Jun 2026 17:32:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781717563; bh=/SQnDjjaa+ApH6wWe2aDhouAw1YQxs5X6sfF4wLVHvU=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=iiQ6eNI/nnjbSO/YiFX5Z05kujMeruwBw0+D0I3irkhPEXHBEwgvQuNehBpvRi0Wp ji2Uv46GGloJnMYpT6oermju1WzdPejwTil41t0iA6brkwIYYqKs4EcNwu4KRtPNJN 5C5B/wm0cbPwO4qs3aJsBW9CrIq+7bV2jJp3PDgijCSTxPq8v49DjBA0z34YiCf44M Mc05gm86Lxgc5dd2NlQO+Ykpu93CyNMnSr0r1Ke42izfeMjUxsPJiTniAmaPyo55fi uJNVejfNyLl9OGFCqBGgtBc1M763qvJJmEDPJK+TMwdcmc+QuT42KA3D+C8rng5oJD 3fVqQv9O8PrsQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wZu80-0000000DlgG-3MYk; Wed, 17 Jun 2026 17:32:40 +0000 Date: Wed, 17 Jun 2026 18:32:40 +0100 Message-ID: <86qzm5rs1z.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Jintack Lim , Ganapatrao Kulkarni , Christoffer Dall , linux-kernel@vger.kernel.org Subject: Re: [PATCH] KVM: arm64: nv: Fix PSTATE construction on illegal exception return In-Reply-To: References: <20260617144907.2972095-1-tabba@google.com> <86se6lru7w.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, jintack.lim@linaro.org, gankulkarni@os.amperecomputing.com, christoffer.dall@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 17 Jun 2026 18:19:20 +0100, Fuad Tabba wrote: > > On Wed, 17 Jun 2026 at 17:45, Marc Zyngier wrote: > > > > On Wed, 17 Jun 2026 15:49:07 +0100, > > Fuad Tabba wrote: > > > > > > kvm_check_illegal_exception_return() sourced the flags {N,Z,C,V} and > > > masks {D,A,I,F} of the resulting PSTATE from the current PSTATE, but > > > R_VWJHB takes them from the SPSR being returned to and leaves > > > PSTATE.{EL,SP,nRW} (and EXLOCK when FEAT_GCS) unchanged. PAN, ALLINT > > > and PM were not applied at all. > > > > > > Build the PSTATE by taking those fields from the SPSR while preserving > > > EL, SP, nRW and EXLOCK from the current PSTATE, then set IL. > > > > > > Fixes: 47f3a2fc765a ("KVM: arm64: nv: Support virtual EL2 exceptions") > > > Suggested-by: Marc Zyngier > > > Link: https://lore.kernel.org/all/86wlvxs5r0.wl-maz@kernel.org/ > > > Signed-off-by: Fuad Tabba > > > --- > > > This is a modified version of Marc's suggested diff [1]. That diff applied > > > a single mask to the incoming SPSR, which also takes PSTATE.{EL,SP,nRW} > > > (and EXLOCK) from the SPSR. The ARM ARM leaves those fields unchanged on an > > > illegal exception return. This path is reached precisely because SPSR.M is > > > illegal (EL3, M[1]=1, AArch32, EL1 under TGE), so this version preserves > > > EL/SP/nRW/EXLOCK from the current PSTATE and takes only the flags, masks > > > and PAN/ALLINT/PM from the SPSR. > > > > > > [1] https://lore.kernel.org/all/86wlvxs5r0.wl-maz@kernel.org/ > > > --- > > > arch/arm64/kvm/emulate-nested.c | 33 +++++++++++++++++++++++---------- > > > 1 file changed, 23 insertions(+), 10 deletions(-) > > > > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > > index dba7ced74ca5..ace2b40cf875 100644 > > > --- a/arch/arm64/kvm/emulate-nested.c > > > +++ b/arch/arm64/kvm/emulate-nested.c > > > @@ -2738,17 +2738,30 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > > (spsr & PSR_MODE32_BIT) || > > > (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || > > > mode == PSR_MODE_EL1h))) { > > > - /* > > > - * The guest is playing with our nerves. Preserve EL, SP, > > > - * masks, flags from the existing PSTATE, and set IL. > > > - * The HW will then generate an Illegal State Exception > > > - * immediately after ERET. > > > - */ > > > - spsr = *vcpu_cpsr(vcpu); > > > + u64 cpsr = *vcpu_cpsr(vcpu); > > > + u64 mask; > > > > > > - spsr &= (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | > > > - PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT | > > > - PSR_MODE_MASK | PSR_MODE32_BIT); > > > + /* > > > + * On an illegal exception return, PSTATE.{EL,SP,nRW} and, > > > + * if FEAT_GCS, PSTATE.EXLOCK are unchanged, while the flags > > > + * and masks are taken from the SPSR (R_VWJHB). Set IL so the > > > + * HW generates an Illegal State Exception right after ERET. > > > + */ > > > + mask = PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | > > > + PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; > > > + > > > + if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, PAN, IMP)) > > > + mask |= PSR_PAN_BIT; > > > + if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, NMI, IMP)) > > > + mask |= ALLINT_ALLINT; > > > + /* FEAT_SPE_EXC and FEAT_TRBE_EXC also gate PSTATE.PM one day... */ > > > + if (kvm_has_feat(vcpu->kvm, ID_AA64DFR1_EL1, EBEP, IMP)) > > > + mask |= BIT_ULL(32); /* PSTATE.PM */ > > > + > > > + spsr &= mask; > > > + spsr |= cpsr & (PSR_MODE_MASK | PSR_MODE32_BIT); > > > + if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) > > > + spsr |= cpsr & BIT_ULL(34); /* PSTATE.EXLOCK */ > > > spsr |= PSR_IL_BIT; > > > } > > > > While I'm happy that you caught the bugs I left for you to address, > > the overall structure is a bit inconsistent. I'd like to have: > > > > - a mask of the bits we preserve from SPSR, and apply that to SPSR > > itself > > > > - a mask of the bits we preserve from PSTATE, and transfer them to > > SPSR > > > > - the comment at the top to describe this in that particular order. > > > > With that, I reworked your patch as follows: > > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > index bb335fa16f7cc..243e5e26f7018 100644 > > --- a/arch/arm64/kvm/emulate-nested.c > > +++ b/arch/arm64/kvm/emulate-nested.c > > @@ -2746,14 +2746,14 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > (spsr & PSR_MODE32_BIT) || > > (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || > > mode == PSR_MODE_EL1h))) { > > - u64 cpsr = *vcpu_cpsr(vcpu); > > u64 mask; > > > > /* > > - * On an illegal exception return, PSTATE.{EL,SP,nRW} and, > > - * if FEAT_GCS, PSTATE.EXLOCK are unchanged, while the flags > > - * and masks are taken from the SPSR (R_VWJHB). Set IL so the > > - * HW generates an Illegal State Exception right after ERET. > > + * On an illegal exception return, the flags and masks are > > + * taken from the SPSR while PSTATE.{EL,SP,nRW} and, if > > + * FEAT_GCS, PSTATE.EXLOCK are unchanged (R_VWJHB). Set IL > > + * so the HW generates an Illegal State Exception right > > + * after ERET. > > */ > > mask = PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | > > PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT; > > @@ -2767,9 +2767,12 @@ static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > mask |= BIT_ULL(32); /* PSTATE.PM */ > > > > spsr &= mask; > > - spsr |= cpsr & (PSR_MODE_MASK | PSR_MODE32_BIT); > > + > > + mask = PSR_MODE_MASK | PSR_MODE32_BIT; > > if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) > > - spsr |= cpsr & BIT_ULL(34); /* PSTATE.EXLOCK */ > > + mask |= BIT_ULL(34); /* PSTATE.EXLOCK */ > > + > > + spsr |= *vcpu_cpsr(vcpu) & mask; > > spsr |= PSR_IL_BIT; > > } > > > > Does that work for you? > > Yes, that's cleaner, thanks. The two-mask form (take from SPSR, then > preserve from PSTATE) reads better than my interleaved version. > > Would you like me to send a v2 (which would be identical to the above? > :) ), or would you fold it in? I've squashed that in. Thanks, M. -- Without deviation from the norm, progress is not possible.