From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE58AFF8868 for ; Tue, 28 Apr 2026 14:57:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HaMwJ5pw1dugp2h+3Jo3Q9ADwxPWGEGVvQfRV1ZUYgk=; b=3JpE+oTBA7UoGt9nwgk0McTeRb 9Ox6EBnL6zrSuwwBRzt1KOZ7tLI7FIqHfpy6+2lutSvklUJcWU83r8ISc9hzIz8KNdo58+gySwCT1 kU1fAQwtHWzlu39S3WeS9ilvn9xF1sx+biXJKdMPMKNz5yL0ytUG0khHOPfpocrOTEWcgL10DWjh4 eKSa0C4lWkYJ+9x+dnN9uwfXUPVGYQcKBuX3KQtM/Stqn7EdkUcXFuOWYRMvyMWMmlAmZo1jUEtmV LCulcB0hGlCvFxvqCq4GCRkJHGEtgAF2w8EGOCbp4ftC/W71VUdcozITMXmb6Bci+Qi+2itxeRegl MXTYYWFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wHjrq-00000001h7k-3sxU; Tue, 28 Apr 2026 14:56:54 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1wHjrq-00000001h7e-17fI for linux-arm-kernel@lists.infradead.org; Tue, 28 Apr 2026 14:56:54 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 6168861146; Tue, 28 Apr 2026 14:56:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 102A5C2BCB5; Tue, 28 Apr 2026 14:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777388213; bh=YVMCAkCkVuCXxr4YLY8bi/zWdrSnhneLvdiGU/6OtME=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jkatepTCvLfkM2z9Z/V4asFQmL8vVMnOfFwT44HuOn2mjCfoRZEJmHvRWvvdB8fDp IW00paivTQzxzFt7YHulUtDiB3qNjGMvyTlz7Qrk0ic0RsPXrrslrpFMOvSwyC2Yr0 JdR3y6HrqQ2d+M2kLePPAr02vI7TKjtUWiaXqfyfYegZ+syQK7+WLiCfcFXNXKsmZX 2xkZTlJKYXHnXPwOhRXDb5VJ0b8SIDb8FFHa2IBdHYGA0X/KwuOo3YY5KNmgOejvvC OMMumI0tpQU/BGDsHvPbD81hfLPvN5Xwc7O40x2gk3yZcd558e1tXBkaLGpYNOWqiI 8HIJ+csRUBVqg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wHjrm-0000000FYDW-1gtE; Tue, 28 Apr 2026 14:56:50 +0000 Date: Tue, 28 Apr 2026 15:56:50 +0100 Message-ID: <86qznzyvyl.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 04/43] irqchip/gic-v5: Provide IRS config frame attrs to KVM In-Reply-To: <20260427160547.3129448-5-sascha.bischoff@arm.com> References: <20260427160547.3129448-1-sascha.bischoff@arm.com> <20260427160547.3129448-5-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 27 Apr 2026 17:07:24 +0100, Sascha Bischoff wrote: > > KVM needs to interact with the host IRS in order to, for example, make > VMs or VPEs valid. There are two potential approaches here. Either the > host irqchip driver can provide an interface, or KVM can interact > directly with the host IRS. The latter of these two is chosen as the > set of MMIO registers that KVM needs to interact with is orthogonal to > the set used by the host irqchip driver (with the exception of some of > the read-only IRS_IDRx registers). > > Pass KVM a pointer to an IRS config frame - the config frame belonging > to ANY IRS is fine as long as one IRS's config frame is used > consistently - in struct gic_kvm_info. Additionally, include a flag > telling KVM whether the IRS is coherent or non-coherent in order to > make sure that KVM can do the correct cache state management, if > required. > > Signed-off-by: Sascha Bischoff > --- > drivers/irqchip/irq-gic-v5-irs.c | 26 ++++++++++++++++++++++++++ > drivers/irqchip/irq-gic-v5.c | 3 +++ > include/linux/irqchip/arm-gic-v5.h | 2 ++ > include/linux/irqchip/arm-vgic-info.h | 5 +++++ > 4 files changed, 36 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c > index f3fce0b1e25d9..5dfa043cf9e34 100644 > --- a/drivers/irqchip/irq-gic-v5-irs.c > +++ b/drivers/irqchip/irq-gic-v5-irs.c > @@ -50,6 +50,32 @@ static void irs_writeq_relaxed(struct gicv5_irs_chip_data *irs_data, > writeq_relaxed(val, irs_data->irs_base + reg_offset); > } > > +void __iomem *gicv5_irs_get_config_frame_base(void) > +{ > + struct gicv5_irs_chip_data *irs_data = per_cpu(per_cpu_irs_data, > + smp_processor_id()); > + > + if (!irs_data) > + return NULL; > + > + return irs_data->irs_base; > +} > + > +bool gicv5_irs_is_non_coherent(void) > +{ > + struct gicv5_irs_chip_data *irs_data = per_cpu(per_cpu_irs_data, > + smp_processor_id()); > + > + if (!irs_data) { > + pr_err("Failed to look up IRS for CPU %d\n", > + smp_processor_id()); > + return false; > + } > + > + return !!(irs_data->flags & IRS_FLAGS_NON_COHERENT); > +} > + Frankly, we don't need these micro-helpers. Just add *one* that returns a pointer to the IRS data for CPU0, and do the information cherry-picking in the caller. > + > /* > * The polling wait (in gicv5_wait_for_op_s_atomic()) on a GIC register > * provides the memory barriers (through MMIO accessors) > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c > index 58e457d4c1476..3329019722360 100644 > --- a/drivers/irqchip/irq-gic-v5.c > +++ b/drivers/irqchip/irq-gic-v5.c > @@ -1134,6 +1134,9 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) > > gic_v5_kvm_info.type = GIC_V5; > > + gic_v5_kvm_info.gicv5_irs.base = gicv5_irs_get_config_frame_base(); > + gic_v5_kvm_info.gicv5_irs.non_coherent = gicv5_irs_is_non_coherent(); > + > /* GIC Virtual CPU interface maintenance interrupt */ > gic_v5_kvm_info.no_maint_irq_mask = false; > gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); While you're at it, you may want to fix the check on the maintenance interrupt, which gives up registering with KVM if no MI is found, even in the absence of FEAT_GCIE_LEGACY. Thanks, M. -- Without deviation from the norm, progress is not possible.