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Fri, 19 Dec 2025 14:13:39 +0000 Date: Fri, 19 Dec 2025 14:13:39 +0000 Message-ID: <86qzsqmuek.wl-maz@kernel.org> From: Marc Zyngier To: Leonardo Bras Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Alexandru Elisei , Sascha Bischoff , Quentin Perret , Fuad Tabba , Sebastian Ene Subject: Re: [PATCH v2 1/6] KVM: arm64: Fix EL2 S1 XN handling for hVHE setups In-Reply-To: References: <20251210173024.561160-1-maz@kernel.org> <20251210173024.561160-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: leo.bras@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, Sascha.Bischoff@arm.com, qperret@google.com, tabba@google.com, sebastianene@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 19 Dec 2025 13:38:50 +0000, Leonardo Bras wrote: > > On Wed, Dec 10, 2025 at 05:30:19PM +0000, Marc Zyngier wrote: > > The current XN implementation is tied to the EL2 translation regime, > > and fall flat on its face with the EL2&0 one that is used for hVHE, > > as the permission bit for privileged execution is a different one. > > > > Fixes: 6537565fd9b7f ("KVM: arm64: Adjust EL2 stage-1 leaf AP bits when ARM64_KVM_HVHE is set") > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_pgtable.h | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > > index fc02de43c68dd..be68b89692065 100644 > > --- a/arch/arm64/include/asm/kvm_pgtable.h > > +++ b/arch/arm64/include/asm/kvm_pgtable.h > > @@ -87,7 +87,15 @@ typedef u64 kvm_pte_t; > > > > #define KVM_PTE_LEAF_ATTR_HI_SW GENMASK(58, 55) > > > > -#define KVM_PTE_LEAF_ATTR_HI_S1_XN BIT(54) > > +#define __KVM_PTE_LEAF_ATTR_HI_S1_XN BIT(54) > > +#define __KVM_PTE_LEAF_ATTR_HI_S1_UXN BIT(54) > > +#define __KVM_PTE_LEAF_ATTR_HI_S1_PXN BIT(53) > > + > > +#define KVM_PTE_LEAF_ATTR_HI_S1_XN \ > > + ({ cpus_have_final_cap(ARM64_KVM_HVHE) ? \ > > + (__KVM_PTE_LEAF_ATTR_HI_S1_UXN | \ > > + __KVM_PTE_LEAF_ATTR_HI_S1_PXN) : \ > > + __KVM_PTE_LEAF_ATTR_HI_S1_XN; }) > > > > #define KVM_PTE_LEAF_ATTR_HI_S2_XN GENMASK(54, 53) > > > > -- > > 2.47.3 > > > > Cool, > Is this according to the following in Arm ARM? > > Figure D8-16 > Stage 1 attribute fields in VMSAv8-64 Block and Page descriptors In M.a (or M.a.a, as it is now called), this is all part of I_GLMLD. But R_JJNHR is a much more interesting source of information, as it clearly outlines in which conditions XN, UXN and PXN are all sharing the same two bits in funky ways... Thanks, M. -- Without deviation from the norm, progress is not possible.