From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B87ACCD19A for ; Tue, 18 Nov 2025 08:54:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SHM2EAFPcEcla99BgcP6PX4+E1f5noDF+87qAHpuFQ8=; b=OXUjk3ybF8Hv4Y6zUKiTLfB3Bg UsO6c+GQ4m/ENYwpRtZfMLOLPpRUeyn7099cN/+6JIX3U50Gn8UzPyYY8W1Ubr/z7a0srF0yG5N1v hMCHv0/xTrfq+aZ4nAXQ/3ca50e8P7HDtbM68Pljz4XSgf3XG+tvdIAExq0JBZsZqFHtCF1Eibnsp pgIe9c8Ggyf49bFsXvkqTozFBuYA0yMAXOpyBu3v2R8BzBi+D8kz7fk1Fqj9M9kiO2DeT0W1XAd/0 J0WSsVjkf0P1HluO9mhCUjcC0NCfZ9/8XuONS1gL2Su77Ct2WLf+6ulCuSkTW85UywoZ5Uwlz1fYr oRZdNz6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vLHU0-0000000073S-4A96; Tue, 18 Nov 2025 08:54:40 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vLHTz-0000000072I-3ACB for linux-arm-kernel@lists.infradead.org; Tue, 18 Nov 2025 08:54:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id AF2F760192; Tue, 18 Nov 2025 08:54:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DE5EC2BD01; Tue, 18 Nov 2025 08:54:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763456078; bh=qREI2xZBKFk1AaWq3n7qoCSnNHV94Pp8p3hmarr/YqQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cXGOjKpTgtfc3OdAYfQEuU4xeHg2KPYFPO96LoPVEvnIoWn4zX3+iIUrW6VL5Hhzz CCIr9/iq1B/mDuGrO2ZjIVmIX+byjuMw6D3DRl0tTpHEvNj81IyZgP9yNgf6K3DejQ 2br9SEEaqk9NRGvTFcGEGzFbtaZo0c63VfBA76zk8uc7eQLFwIwULHBaZ7hppYpmBv tcTRuI/vfpXv7JcQvg3Jy4BCQ+5QLfClHjFZLdIy7WsySl4pq/aU5PKd4Mof99Rkag 5DbYym86K6BwfO72enHkFqi8PLLpdPW6+sPYaNnxsBJvWSaEBs4zuClhOx1lu+KCzX fcjhun9OG/3rw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vLHTq-000000067I6-0f34; Tue, 18 Nov 2025 08:54:30 +0000 Date: Tue, 18 Nov 2025 08:54:29 +0000 Message-ID: <86qztvsou2.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Christoffer Dall , Fuad Tabba , Mark Brown Subject: Re: [PATCH v3 5/5] KVM: arm64: GICv3: Force exit to sync ICH_HCR_EL2.En In-Reply-To: References: <20251117091527.1119213-1-maz@kernel.org> <20251117091527.1119213-6-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, christoffer.dall@arm.com, tabba@google.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 18 Nov 2025 07:16:49 +0000, Oliver Upton wrote: > > Hey Marc, > > On Mon, Nov 17, 2025 at 09:15:27AM +0000, Marc Zyngier wrote: > > FEAT_NV2 is pretty terrible for anything that tries to enforce immediate > > effects, and writing to ICH_HCR_EL2 in the hope to disable a maintenance > > interrupt is vain. This only hits memory, and the guest hasn't cleared > > anything -- the MI will fire. > > > > For example, running the vgic_irq test under NV results in about 800 > > maintenance interrupts being actually handled by the L1 guest, > > when none were expected. > > > > As a cheap workaround, read back ICH_MISR_EL2 after writing 0 to > > ICH_HCR_EL2. This is very cheap on real HW, and causes a trap to > > the host in NV, giving it the opportunity to retire the pending > > MI. With this, the above test tuns to completion without any MI > > being actually handled. > > Just to make sure I'm following, the scenario you're talking about is > we've already put the vgic into a non-nested state, populated an LR with > the pending MI at the time of that switch and L0 has no signal for when > it can drop the LR / pending state. Exactly. Only an exit can cause it to reevaluate the state and retire the pending MI. > > > Yes, this is really poor... > > +1 :-/ > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/vgic-v3-sr.c | 7 +++++++ > > arch/arm64/kvm/vgic/vgic-v3-nested.c | 6 ++++-- > > 2 files changed, 11 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c > > index 99342c13e1794..f503cf01ac82c 100644 > > --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c > > +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c > > @@ -244,6 +244,13 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if) > > } > > > > write_gicreg(0, ICH_HCR_EL2); > > + > > + /* > > + * Hack alert: On NV, this results in a trap so that the above > > + * write actually takes effect... > > + */ > > + isb(); > > + read_gicreg(ICH_MISR_EL2); > > I'm all for writing correct code but since we don't actually care about > the value of MISR_EL2 do we need the ISB? There's no need for a CSE for > non-NV and you'd get it 'for free' by way of exception entry in the NV > case. Yup, that's a good point. And exceptions are of course guaranteed to be in program order anyway, so the ISB can go. I'll add comment to that effect. Thanks, M. -- Without deviation from the norm, progress is not possible.