From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CE1DC5478C for ; Fri, 23 Feb 2024 11:07:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YsxJmSttIbndeldWaYPW68u6xOuJttE1OAL57MTjGmw=; b=P0HmZ5h5Mw55Mz 3/BDakgq7Ufof3aKRdU6TzmHdvsDnr942qvKQr4yILEfZHS5+9ucc0Y3H9O6hfuyROqo4Yy7cAdnT 1IbdQ/e7sULwhJPETujx8tj2bl/KOkvJoW4h/qalWo08Tr7qQuhVmEpi2XX6MtCzTpD/nyEkQCF9O dptJ4MW4sZlalY7oUJ/4RHCnKexaATuPbXk84dT8KfE/R7LxS/PAp1kIb+rrizff/BBTSC9Cq/+aM VFjPzKwX/PJaG8DZo8N++BX7R+fMqADbXjcHBQfNovXNGDzmhYMB2wST2G8gftX9pUcxJcvRUp4k2 R/73YFy6vJpDw38eb/Cg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rdTOd-000000094SX-1Cze; Fri, 23 Feb 2024 11:07:17 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rdTOW-000000094Qj-3ple for linux-arm-kernel@lists.infradead.org; Fri, 23 Feb 2024 11:07:10 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 67491CE2B11; Fri, 23 Feb 2024 11:07:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 801FEC433F1; Fri, 23 Feb 2024 11:07:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708686425; bh=Zlm5d+QOs/dktmMB+z0HKv98GRZBJLPrBX3i8rbARso=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YAY3CJ5bB/KTy3+uDviC3rtHYpB5iZfKlvwFkPvcAsCbAFqyHYEYXThiV5Q5CMHhU j5a/GSSWxeub66LHvHTcWC1N3NXCWGn20UypDl00hL9UgnGxrInbr2ZidAuHyeXeqw xNAIC7vv+mTbC2hJfCSPozSvRc8xsz+XBtiFHtfBemd0JweUDx4bd9K2ICMO+ej5Mm HrLtBXBI/SnCHRRpmQAS8LrnLY+D7Mkl6kav5DgOjqhO8Gnt4Cb/39B49kgjdGrTD5 RZPw6nxk2uPRXpZd7t8Hmui1cIq3Hpf5kVfj9qHwZr5TLhQ7QeB1lOYg2KY9kGFN+p uf98LxxIE3b2w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rdTOQ-0063wt-P7; Fri, 23 Feb 2024 11:07:03 +0000 Date: Fri, 23 Feb 2024 11:07:02 +0000 Message-ID: <86r0h330dl.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v4 03/14] arm64/fpsimd: Support FEAT_FPMR In-Reply-To: <20240122-arm64-2023-dpisa-v4-3-776e094861df@kernel.org> References: <20240122-arm64-2023-dpisa-v4-0-776e094861df@kernel.org> <20240122-arm64-2023-dpisa-v4-3-776e094861df@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, corbet@lwn.net, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dave.martin@arm.com, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240223_030709_507109_228D4327 X-CRM114-Status: GOOD ( 34.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 22 Jan 2024 16:28:06 +0000, Mark Brown wrote: > > FEAT_FPMR defines a new EL0 accessible register FPMR use to configure the > FP8 related features added to the architecture at the same time. Detect > support for this register and context switch it for EL0 when present. > > Due to the sharing of responsibility for saving floating point state > between the host kernel and KVM FP8 support is not yet implemented in KVM > and a stub similar to that used for SVCR is provided for FPMR in order to > avoid bisection issues. To make it easier to share host state with the > hypervisor we store FPMR as a hardened usercopy field in uw (along with > some padding). > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/cpufeature.h | 5 +++++ > arch/arm64/include/asm/fpsimd.h | 2 ++ > arch/arm64/include/asm/kvm_host.h | 1 + > arch/arm64/include/asm/processor.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > arch/arm64/kernel/fpsimd.c | 13 +++++++++++++ > arch/arm64/kvm/fpsimd.c | 1 + > arch/arm64/tools/cpucaps | 1 + > 8 files changed, 36 insertions(+) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 21c824edf8ce..34fcdbc65d7d 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -768,6 +768,11 @@ static __always_inline bool system_supports_tpidr2(void) > return system_supports_sme(); > } > > +static __always_inline bool system_supports_fpmr(void) > +{ > + return alternative_has_cap_unlikely(ARM64_HAS_FPMR); > +} > + > static __always_inline bool system_supports_cnp(void) > { > return alternative_has_cap_unlikely(ARM64_HAS_CNP); > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index 50e5f25d3024..6cf72b0d2c04 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -89,6 +89,7 @@ struct cpu_fp_state { > void *sve_state; > void *sme_state; > u64 *svcr; > + unsigned long *fpmr; > unsigned int sve_vl; > unsigned int sme_vl; > enum fp_type *fp_type; > @@ -154,6 +155,7 @@ extern void cpu_enable_sve(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_sme(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused); > +extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused); > > extern u64 read_smcr_features(void); > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 21c57b812569..7993694a54af 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -543,6 +543,7 @@ struct kvm_vcpu_arch { > enum fp_type fp_type; > unsigned int sve_max_vl; > u64 svcr; > + unsigned long fpmr; As this directly represents a register, I'd rather you use a type that represents the size of that register unambiguously (u64). > > /* Stage 2 paging state used by the hardware on next switch */ > struct kvm_s2_mmu *hw_mmu; > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 5b0a04810b23..b453c66d3fae 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -155,6 +155,8 @@ struct thread_struct { > struct { > unsigned long tp_value; /* TLS register */ > unsigned long tp2_value; > + unsigned long fpmr; > + unsigned long pad; > struct user_fpsimd_state fpsimd_state; > } uw; > > @@ -253,6 +255,8 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, > BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != > sizeof_field(struct thread_struct, uw.tp_value) + > sizeof_field(struct thread_struct, uw.tp2_value) + > + sizeof_field(struct thread_struct, uw.fpmr) + > + sizeof_field(struct thread_struct, uw.pad) + > sizeof_field(struct thread_struct, uw.fpsimd_state)); > > *offset = offsetof(struct thread_struct, uw); > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index eae59ec0f4b0..0263565f617a 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -272,6 +272,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), > ARM64_FTR_END, > }; > > @@ -2767,6 +2768,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_lpa2, > }, > + { > + .desc = "FPMR", > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .capability = ARM64_HAS_FPMR, > + .matches = has_cpuid_feature, > + .cpu_enable = cpu_enable_fpmr, > + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) > + }, > {}, > }; > > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c > index a5dc6f764195..8e24b5e5e192 100644 > --- a/arch/arm64/kernel/fpsimd.c > +++ b/arch/arm64/kernel/fpsimd.c > @@ -359,6 +359,9 @@ static void task_fpsimd_load(void) > WARN_ON(preemptible()); > WARN_ON(test_thread_flag(TIF_KERNEL_FPSTATE)); > > + if (system_supports_fpmr()) > + write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR); > + > if (system_supports_sve() || system_supports_sme()) { > switch (current->thread.fp_type) { > case FP_STATE_FPSIMD: > @@ -446,6 +449,9 @@ static void fpsimd_save_user_state(void) > if (test_thread_flag(TIF_FOREIGN_FPSTATE)) > return; > > + if (system_supports_fpmr()) > + *(last->fpmr) = read_sysreg_s(SYS_FPMR); > + > /* > * If a task is in a syscall the ABI allows us to only > * preserve the state shared with FPSIMD so don't bother > @@ -688,6 +694,12 @@ static void sve_to_fpsimd(struct task_struct *task) > } > } > > +void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__always_unused p) > +{ > + write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK, > + SYS_SCTLR_EL1); > +} > + > #ifdef CONFIG_ARM64_SVE > /* > * Call __sve_free() directly only if you know task can't be scheduled > @@ -1680,6 +1692,7 @@ static void fpsimd_bind_task_to_cpu(void) > last->sve_vl = task_get_sve_vl(current); > last->sme_vl = task_get_sme_vl(current); > last->svcr = ¤t->thread.svcr; > + last->fpmr = ¤t->thread.uw.fpmr; > last->fp_type = ¤t->thread.fp_type; > last->to_save = FP_STATE_CURRENT; > current->thread.fpsimd_cpu = smp_processor_id(); > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > index 8c1d0d4853df..e3e611e30e91 100644 > --- a/arch/arm64/kvm/fpsimd.c > +++ b/arch/arm64/kvm/fpsimd.c > @@ -153,6 +153,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) > fp_state.sve_vl = vcpu->arch.sve_max_vl; > fp_state.sme_state = NULL; > fp_state.svcr = &vcpu->arch.svcr; > + fp_state.fpmr = &vcpu->arch.fpmr; > fp_state.fp_type = &vcpu->arch.fp_type; Given the number of fields you keep track of, it would make a lot more sense if these FP-related fields were in their own little structure and tracked by a single pointer (I don't think there is a case where we track them independently). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel