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Tue, 27 Oct 2026 16:44:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793119453; bh=nx17FIAQCfOlFkP17EZEoi5gViilW8Y7/HSO+vAKVsw=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=d/gf83wvfXAhjxM5t1yPfeZXqDU0qDuWGm2q+pJ72nQhojJ7vCMmngQcQix56nhYC 6Xezdj3m6GEpl35gmKf4SG3W8X6BYFzOmoSKWGlZNMdkSWW4vOokAvdeEeENXKDU4X 3CfCOkNJohOJxcl4gWf+/m9kYb+BS7LmckkyVLWy7PTi3ZbEWFCzEwpc5u1lNSrwRp X0FE8aFBk2PWFTJxd3Zzpxia+2d30yB0Gq8QEx1qWlYeDe82ebBD90W4NSa5Unlcx5 FfzyJhFf0G+loppwSMVkbb6sC8v3de2UwiY1a+RJZM+UgIQLYQfgWhaMiqcRmf4lDy zDKUuf55D2WrA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xLkHS-00000007oLP-2Vpc; Tue, 27 Oct 2026 16:44:10 +0000 Date: Tue, 27 Oct 2026 16:44:10 +0000 Message-ID: <86se1rxfdx.wl-maz@kernel.org> From: Marc Zyngier To: Amir Noohi Cc: Thomas Gleixner , Oliver Upton , Radu Rendec , Igor Velkov , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Christoffer Dall , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] genirq/manage: Provide irq_set_percpu_irqchip_state() In-Reply-To: <20261024212844.3405617-1-amirmnoohi@gmail.com> References: <20261024022450.629980-1-amirmnoohi@gmail.com> <20261024022450.629980-2-amirmnoohi@gmail.com> <87se1v8f2r.wl-maz@kernel.org> <20261024212844.3405617-1-amirmnoohi@gmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Archived-By: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: amirmnoohi@gmail.com, tglx@kernel.org, oupton@kernel.org, radu@rendec.net, iav@iav.lv, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, cdall@linaro.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Sat, 24 Oct 2026 22:28:44 +0100, Amir Noohi wrote: > > Hi Marc, > > On Sat, 24 Oct 2026 13:21:00 +0100, Marc Zyngier wrote: > > It really feels like a leap of faith. > > > > There is nothing that says that it is safe to call this without > > holding the global lock. For all we know, drivers have been relying on > > it for a good decade, and I don't feel confident letting things rip > > just because it (mostly) works with the GIC. > > > > At the very least, something exposed by the irqchip (a per-IRQ flag?) > > should tell you whether it is safe to elide the lock. > > Agreed, and v2 does that. There's a new IRQCHIP_PERCPU_STATE_LOCKLESS > flag, and irq_set_percpu_irqchip_state() only skips the descriptor lock > if the chip implementing irq_set_irqchip_state() has it set. Otherwise, > or if there's a bus lock, it just calls irq_set_irqchip_state(), so > drivers that don't opt in see no change. I'm not sure this is the correct option. Making it per irqchip is again assuming that the irqchip has a uniform handling of the state across all interrupts. I'm afraid that's not universally true, which is why I hinted at a per-IRQ flag. Alternatively, you can audit all the providers of this API and work out if is it safe to do so, and split the corresponding callbacks. Good luck with that. :-/ > > Only GICv3 sets it, in a separate patch. For SGIs/PPIs/EPPIs its > callback only touches the local redistributor (gic_data_rdist_sgi_base() > and the RWP poll), nothing shared. Read the code again. There is *one* callback for all distributor-owned interrupts, which also involves SPIs/ESPIs. > FWIW, irq-gic.c, irq-gic-v3.c and > irq-gic-v5.c are the only drivers with both per-CPU devid interrupts and > an irq_set_irqchip_state() callback. KVM's own timer chip (GICv5, no HW > deactivation) doesn't set it either, so those keep the lock. The KVM chip inherits whatever it is pushed upon, and it is still a per-CPU interrupt. To be clear, this is an all or nothing approach as far as KVM is concerned, so anything that KVM uses should be converted to the lockless approach. Even in the GICv5 case, the ICC_PPI_ENABLER0 register cannot be modified concurrently, so it should be safe to advertise these as lockless. > > On GICv2 in QEMU it still takes the lock like mainline does (333k vs > 321k acquisitions in lock_stat, within 4%), and on GICv3 it doesn't > take it at all. arch_timer, arch_timer_edge_cases, vgic_irq and > vgic_init pass on the Altra. Under QEMU with lockdep, DEBUG_PREEMPT and > DEBUG_ATOMIC_SLEEP, the selftests pass on GICv3 (VHE and nVHE) and > GICv2 (the vGICv3 ones skip there). No splats. > > I made it a chip flag since it's about the callback, but I can make it > per-IRQ if you prefer. I reckon this is a requirement. Thanks, M. -- Without deviation from the norm, progress is not possible.