From: Marc Zyngier <maz@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: Sascha Bischoff <Sascha.Bischoff@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>
Subject: Re: [PATCH v7 12/41] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE
Date: Tue, 24 Mar 2026 14:48:04 +0000 [thread overview]
Message-ID: <86se9p472z.wl-maz@kernel.org> (raw)
In-Reply-To: <638a3453-91c9-4a76-8241-25d5c27ca518@sirena.org.uk>
On Tue, 24 Mar 2026 12:47:24 +0000,
Mark Brown <broonie@kernel.org> wrote:
>
> [1 <text/plain; us-ascii (7bit)>]
> On Thu, Mar 19, 2026 at 03:52:50PM +0000, Sascha Bischoff wrote:
> > Add in a sanitization function for ID_AA64PFR2_EL1, preserving the
> > already-present behaviour for the FPMR, MTEFAR, and MTESTOREONLY
> > fields. Add sanitisation for the GCIE field, which is set to IMP if
> > the host supports a GICv5 guest and NI, otherwise.
>
> We're also seeing an issue with this in the aarch32_id_regs test:
>
> # selftests: kvm: aarch32_id_regs
> # Random seed: 0x6b8b4567
> # ==== Test Assertion Failure ====
> # arm64/aarch32_id_regs.c:25: read_sysreg_s((((3) << 19) | ((0) << 16) | ((0) << 12) | ((1) << 8) | ((1) << 5))) == 0
> # pid=3111 tid=3111 errno=4 - Interrupted system call
> # sh: 1: addr2line: not found
> # 0x10000000 != 0x0 (read_sysreg_s((((3) << 19) | ((0) << 16) | ((0) << 12) | ((1) << 8) | ((1) << 5))) != 0)
> not ok 9 selftests: kvm: aarch32_id_regs # exit=254
>
> which for some reason only manifests on TX2 of the platforms I've
> seen.
Is your TX2 the only machine you have that is AArch64 only at all ELs?
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2026-03-24 14:48 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 15:49 [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
2026-03-19 15:49 ` [PATCH v7 01/41] KVM: arm64: vgic-v3: Drop userspace write sanitization for ID_AA64PFR0.GIC on GICv5 Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 02/41] KVM: arm64: vgic: Rework vgic_is_v3() and add vgic_host_has_gicvX() Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 03/41] KVM: arm64: Return early from kvm_finalize_sys_regs() if guest has run Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 04/41] KVM: arm64: Init vcpu prior to the timers and PMU Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 05/41] KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 06/41] arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 07/41] arm64/sysreg: Add GICR CDNMIA encoding Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 08/41] KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 09/41] KVM: arm64: gic: Introduce interrupt type helpers Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 10/41] KVM: arm64: gic-v5: Add Arm copyright header Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 11/41] KVM: arm64: gic-v5: Detect implemented PPIs on boot Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 12/41] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE Sascha Bischoff
2026-03-23 13:37 ` Mark Brown
2026-03-23 13:50 ` Marc Zyngier
2026-03-23 14:08 ` Mark Brown
2026-03-23 17:59 ` Marc Zyngier
2026-03-24 12:47 ` Mark Brown
2026-03-24 14:48 ` Marc Zyngier [this message]
2026-03-24 14:53 ` Mark Brown
2026-03-24 15:25 ` Marc Zyngier
2026-03-24 18:16 ` Mark Brown
2026-03-19 15:53 ` [PATCH v7 13/41] KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 14/41] KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 15/41] KVM: arm64: gic-v5: Trap and emulate ICC_IDR0_EL1 accesses Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 16/41] KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 17/41] KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 18/41] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 19/41] KVM: arm64: gic: Introduce queue_irq_unlock to irq_ops Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 20/41] KVM: arm64: gic-v5: Implement PPI interrupt injection Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 21/41] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 22/41] KVM: arm64: gic-v5: Clear TWI if single task running Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 23/41] KVM: arm64: gic-v5: Check for pending PPIs Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 24/41] KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 25/41] KVM: arm64: Introduce set_direct_injection irq_op Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 26/41] KVM: arm64: gic-v5: Implement direct injection of PPIs Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 27/41] KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 28/41] KVM: arm64: gic-v5: Create and initialise vgic_v5 Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 29/41] KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 30/41] irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 31/41] KVM: arm64: gic-v5: Enlighten arch timer for GICv5 Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 32/41] KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 33/41] KVM: arm64: gic: Hide GICv5 for protected guests Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 34/41] KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 35/41] KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 36/41] KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 37/41] KVM: arm64: gic-v5: Probe for GICv5 device Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 38/41] Documentation: KVM: Introduce documentation for VGICv5 Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 39/41] KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Sascha Bischoff
2026-03-19 16:00 ` [PATCH v7 40/41] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest Sascha Bischoff
2026-03-19 16:00 ` [PATCH v7 41/41] KVM: arm64: selftests: Add no-vgic-v5 selftest Sascha Bischoff
2026-03-19 18:26 ` [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support Marc Zyngier
2026-03-19 18:50 ` (subset) " Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86se9p472z.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=Joey.Gouly@arm.com \
--cc=Sascha.Bischoff@arm.com \
--cc=Suzuki.Poulose@arm.com \
--cc=Timothy.Hayes@arm.com \
--cc=broonie@kernel.org \
--cc=jonathan.cameron@huawei.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=nd@arm.com \
--cc=oliver.upton@linux.dev \
--cc=peter.maydell@linaro.org \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox