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Mon, 02 Oct 2023 15:58:52 +0100 Date: Mon, 02 Oct 2023 15:58:50 +0100 Message-ID: <86sf6tnk9h.wl-maz@kernel.org> From: Marc Zyngier To: Kristina Martsenko Cc: Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Vladimir Murzin , Colton Lewis , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/2] KVM: arm64: Support for Arm v8.8 memcpy instructions in KVM guests In-Reply-To: References: <20230922112508.1774352-1-kristina.martsenko@arm.com> <6687f58c-0da9-0583-2dc1-2089f292b745@arm.com> <87fs2xmiof.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kristina.martsenko@arm.com, oliver.upton@linux.dev, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, vladimir.murzin@arm.com, coltonlewis@google.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_075856_973540_85796220 X-CRM114-Status: GOOD ( 30.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 29 Sep 2023 15:51:32 +0100, Kristina Martsenko wrote: > > On 29/09/2023 10:29, Marc Zyngier wrote: > > On Thu, 28 Sep 2023 17:55:39 +0100, > > Kristina Martsenko wrote: > >> > >> On 27/09/2023 07:00, Oliver Upton wrote: > >>> > >>> On Fri, Sep 22, 2023 at 12:25:06PM +0100, Kristina Martsenko wrote: > >>>> Hi, > >>>> > >>>> This is v2 of the series to allow using the new Arm memory copy instructions > >>>> in KVM guests. See v1 for more information [1]. > >>> > >>> > >>> Thanks for sending out the series. I've been thinking about what the > >>> architecture says for MOPS, and I wonder if what's currently in the > >>> Arm ARM is clear enough for EL1 software to be written robustly. > >>> > >>> While HCRX_EL2.MCE2 allows the hypervisor to intervene on MOPS > >>> exceptions from EL1, there's no such control for EL0. So when vCPU > >>> migration occurs EL1 could get an unexpected MOPS exception, even for a > >>> process that was pinned to a single (virtual) CPU implementation. > >>> > >>> Additionally, the wording of I_NXHPS seems to suggest that EL2 handling > >>> of MOPS exceptions is only expected in certain circumstances where EL1 is > >>> incapable of handling an exception. Is the unwritten expectation then > >>> that EL1 software should tolerate 'unexpected' MOPS exceptions from EL1 > >>> and EL0, even if EL1 did not migrate the PE context? > >>> > >>> Perhaps I'm being pedantic, but I'd really like for there to be some > >>> documentation that suggests MOPS exceptions can happen due to context > >>> migration done by a higher EL as that is the only option in the context > >>> of virtualization. > >> > >> That's a good point. This shouldn't affect Linux guests as Linux is > >> always able to handle a MOPS exception coming from EL0. But it would > >> affect any non-Linux guest that pins all its EL0 tasks and doesn't > >> implement a handler. It's not clear to me what the expectation for > >> guests is, I'll ask the architects to clarify and get back to you. > > > > My understanding is that MCE2 should always be set if the hypervisor > > can migrate vcpus across implementations behind EL1's back, and that > > in this context, EL1 never sees such an exception. > > Notice that MCE2 only traps exceptions from EL1, not from EL0. > Exceptions from EL0 always go to EL1. Even if MCE2 is always set, EL1 > will see the exception when the hypervisor migrates the vcpu while the > vcpu is executing a MOPS instruction in EL0. Ah, good point. I stand corrected. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel