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b=sZg1H7Oih6cfY8L5jsDHE0kBYUdM+isavjUlnWXW0Uu4y/6/SoYZZ5bTflSO+KKeG 8/55D6taS0Im03cxerSTsL94EnaiAclL606CRpVXrceyWfYKWnW+nrrV0HFV1C9RbK 89UJTirtOTCUK7SqnCPgTuTRyB5AsPINwhKIAwn2K48lE69mf7WIuW1AXH5QrzA+ew vf16ehBYcwxb8dNFa5cl85uDZsYkI/QlpK8l0TDf8WcbYFt8V9rMi26xR3euwHN3bP lb7wx9kwI2PNCm8UKuIteAkB7JF1FKyJfE61++5gJYR36AP3NhQJLEAdMEG0FMm9cG VJBk5wTGBDdFw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qGhrz-00AT5j-5o; Tue, 04 Jul 2023 16:23:11 +0100 Date: Tue, 04 Jul 2023 16:23:10 +0100 Message-ID: <86sfa3wvj5.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: linux-arm-kernel@lists.infradead.org, Hanks Chen , Cheng-Yuh.Wu@mediatek.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Workaround for GIC-700 erratum 2941627 In-Reply-To: References: <20230704123436.127449-1-lpieralisi@kernel.org> <86ttujwxb1.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, linux-arm-kernel@lists.infradead.org, hanks.chen@mediatek.com, Cheng-Yuh.Wu@mediatek.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230704_082314_544702_DD91CAF9 X-CRM114-Status: GOOD ( 27.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 04 Jul 2023 16:14:03 +0100, Lorenzo Pieralisi wrote: > > On Tue, Jul 04, 2023 at 03:44:50PM +0100, Marc Zyngier wrote: > > Lorenzo, > > > > On Tue, 04 Jul 2023 13:34:36 +0100, > > Lorenzo Pieralisi wrote: > > > > > > +static bool gic_enable_quirk_arm64_2941627(void *data) > > > +{ > > > + /* > > > + * If CPUidle is not enabled the erratum runtime > > > + * conditions can't be hit, since that requires: > > > + * > > > + * - A core entering a deep power state with > > > + * the associated GIC redistributor asleep > > > + * and an IRQ active and pending targeted at it > > > + * - A different core handling the IRQ and > > > + * related GIC operations at the same time > > > + */ > > > + if (!IS_ENABLED(CONFIG_CPU_IDLE)) > > > + return false; > > > > Could this still hit on a system that traps WFI to EL3 and uses this > > as a way to enter a low-power mode? > > That's a valid point, I have not thought about that. If there are set-ups > where this is allowed (and I think it *is* architecturally allowed with > EL3 saving/restoring context and entering a deep power state - if you > asked I suspect you have something concrete in mind :)) this "optimization" > must be removed since we can still hit the bug; that's what I shall do > for v2. I do not have a concrete example of anyone doing that, but the fact that it is possible by the letter of the architecture makes me think that *someone* out there must be inventive enough to do it. So I'd rather take the safe option and *always* enable the workaround. And then someone else can rock up and explain why they don't need it. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel