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Tue, 27 Oct 2026 11:56:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793102203; bh=DHb2CsPrUIo3vqtFvfQJplBTLRjXA1S1CzZYjYK/+VA=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=j7YVK4C1WPUzr4Dag8iJbUBfAkKIel5QJTaamp0T7nPkgv923yXlUiaxQ4BN5BJKU OLIfi2Aq+fdmqVUj1aCbjicDrU7+hk4H6s8nLU5FceV3DkDhHAeJSdGDNRbLPNt4q+ qrNpu87YvaGT7uPXR6SrUkS2bTDmc6jERmpLipW+zl0podvUIGeZG+BdLdD+5cJC6V DLmEEnESffxFpK+2lMvhnfHt2nWhb0FG0rOtOUwtL927Qp3csTogB6F3E3mzN89qAP q1CCsRsHelzgLDQIrbm1sMGgqcXyhIkIvRM07y+sq4HuXTjKsgQY2pE/tm/C0fizeb O4zGfZw8bPNig== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xLfnF-00000007gAA-3RX6; Tue, 27 Oct 2026 11:56:41 +0000 Date: Tue, 27 Oct 2026 11:56:41 +0000 Message-ID: <86tsm7xsp2.wl-maz@kernel.org> From: Marc Zyngier To: Ashok Raj Cc: Vladimir Murzin , linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, lpieralisi@kernel.org, ruanjinjie@huawei.com, liaochang1@huawei.com, Ashok Raj Subject: Re: [PATCH 00/38] arm64: Add support for FEAT_NMI In-Reply-To: References: <20260914102102.68597-1-vladimir.murzin@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Archived-By: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ashok.raj@oss.qualcomm.com, vladimir.murzin@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, lpieralisi@kernel.org, ruanjinjie@huawei.com, liaochang1@huawei.com, ashoraj@qti.qualcomm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Sat, 24 Oct 2026 05:20:16 +0100, Ashok Raj wrote: > > On Mon, Sep 14, 2026 at 11:20:24AM +0100, Vladimir Murzin wrote: > > > FEAT_NMI provides an architected mechanism for supporting non-maskable > > interrupts (NMIs) and less-masked interrupts (LMIs). > > > > Since we already support pseudo-NMIs via priority masking, introducing > > another flavour of NMI on top of the existing infrastructure could > > easily become messy, making the code harder to follow and reason > > about. > > > > To avoid that, this series first makes room for the new NMI "tenant" > > by restructuring the existing exception masking logic (patches 01/38 - > > 15/38) > > > Hi all, > > I am working on arm64 HEST/GHES Type-4 (NMI) support using FEAT_NMI > and GIC NMI support. > > On arm64, the proposed ACPI semantics are that the Type-4 Vector names > one GSI corresponding to an NMI-capable GIC SPI. I've already said all I had to say about encoding the notion of priority in FW tables. > The NMI property belongs > to that SPI, while its target PE is normal mutable GIC routing state > (GICD_IROUTER). This also permits a platform to describe multiple > GHESv2 Type-4 sources, each with a distinct NMI SPI. > > The current Linux GHES implementation registers the interrupt with: > > request_nmi(irq, handler, > IRQF_PERCPU | IRQF_NOBALANCING | > IRQF_NO_THREAD | IRQF_NO_AUTOEN, > ...); > > request_nmi() requires IRQF_PERCPU, which marks the descriptor IRQD_PER_CPU. > Generic CPU-offline IRQ migration then skips it. This makes sense for a > true PPI, but this GHES interrupt is an SPI: if its target CPU is offlined, > GICD_IROUTER may remain pointed at the outgoing PE and notification can > be lost, or possibly it might fail the cpu offline since an interrupt > can't be retargetted. Obviously, the PERCPU flag says exactly that. So if anything needs fixing, it is the GHES driver. > > The GICv3 affinity callback can retarget an NMI-configured SPI: it masks > the SPI, updates GICD_IROUTER, unmasks it, and updates effective > affinity. > > Would maintainers prefer that GHES explicitly retarget these NMI SPIs in a > CPU-hotplug callback while retaining the current request_nmi() contract, > or should genirq gain an explicit routable-NMI SPI registration model that > is not marked IRQD_PER_CPU, but remains excluded from automatic balancing? The question really is: why does the GHES interrupt need to be strictly affine to one given CPU? > In either model, the intended policy is that irqbalance must not move the > interrupt, NOBALANCING achieves this, by preventing userspace from changing the affinity. > but OSPM must be able to retarget the SPI before its target CPU is > removed. Whatever OSPM is... The real question is *WHY* do you need this. What breaks if you let these interrupts be migrated at will? M. -- Without deviation from the norm, progress is not possible.