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Mon, 02 Oct 2023 15:55:35 +0100 Date: Mon, 02 Oct 2023 15:55:33 +0100 Message-ID: <86ttr9nkey.wl-maz@kernel.org> From: Marc Zyngier To: Kristina Martsenko Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Vladimir Murzin , Colton Lewis , linux-kernel@vger.kernel.org, Oliver Upton Subject: Re: [PATCH v2 1/2] KVM: arm64: Add handler for MOPS exceptions In-Reply-To: <0f99fa65-c8c1-5d5c-d9b0-5436b7592656@arm.com> References: <20230922112508.1774352-1-kristina.martsenko@arm.com> <20230922112508.1774352-2-kristina.martsenko@arm.com> <87sf734ofv.wl-maz@kernel.org> <9f731870-ed36-d2e4-378b-f7fbf338ebd6@arm.com> <87h6ndmixh.wl-maz@kernel.org> <0f99fa65-c8c1-5d5c-d9b0-5436b7592656@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kristina.martsenko@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, vladimir.murzin@arm.com, coltonlewis@google.com, linux-kernel@vger.kernel.org, oliver.upton@linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_075540_107773_D9C3DC84 X-CRM114-Status: GOOD ( 37.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 02 Oct 2023 15:06:33 +0100, Kristina Martsenko wrote: > > On 29/09/2023 10:23, Marc Zyngier wrote: > > On Wed, 27 Sep 2023 09:28:20 +0100, > > Oliver Upton wrote: > >> > >> On Mon, Sep 25, 2023 at 04:16:06PM +0100, Kristina Martsenko wrote: > >> > >> [...] > >> > >>>> What is the rationale for advancing the state machine? Shouldn't we > >>>> instead return to the guest and immediately get the SS exception, > >>>> which in turn gets reported to userspace? Is it because we rollback > >>>> the PC to a previous instruction? > >>> > >>> Yes, because we rollback the PC to the prologue instruction. We advance the > >>> state machine so that the SS exception is taken immediately upon returning to > >>> the guest at the prologue instruction. If we didn't advance it then we would > >>> return to the guest, execute the prologue instruction, and then take the SS > >>> exception on the middle instruction. Which would be surprising as userspace > >>> would see the middle and epilogue instructions executed multiple times but not > >>> the prologue. > >> > >> I agree with Kristina that taking the SS exception on the prologue is > >> likely the best course of action. Especially since it matches the > >> behavior of single-stepping an EL0 MOPS sequence with an intervening CPU > >> migration. > >> > >> This behavior might throw an EL1 that single-steps itself for a loop, > >> but I think it is impossible for a hypervisor to hide the consequences > >> of vCPU migration with MOPS in the first place. > >> > >> Marc, I'm guessing you were most concerned about the former case where > >> the VMM was debugging the guest. Is there something you're concerned > >> about I missed? > > > > My concern is not only the VMM, but any userspace that perform > > single-stepping. Imagine the debugger tracks PC by itself, and simply > > increments it by 4 on a non-branch, non-fault instruction. > > > > Move the vcpu or the userspace around, rewind PC, and now the debugger > > is out of whack with what is executing. While I agree that there is > > not much a hypervisor can do about that, I'm a bit worried that we are > > going to break existing SW with this. > > > > Now the obvious solution is "don't do that"... > > If the debugger can handle the PC changing on branching or faulting > instructions, then why can't it handle it on MOPS instructions? Wouldn't > such a debugger need to be updated any time the architecture adds new > branching or faulting instructions? What's different here? What is different is that we *go back* in the instruction stream, which is a first. I'm not saying that the debugger I describe above would be a very clever piece of SW, quite the opposite. But the way the architecture works results in some interesting side-effects, and I'm willing to bet that some SW will break (rr?). But again, asymmetric systems are such a bad idea that I can't say I care. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel