[PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps

[PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps

[Fuad Tabba]

Changes from v2:
- Rebased on arm64/for-next/sysregs, which includes new system
  register definitions (Mark, Joey)
- Explicitly trap unsupported HFGxTR_EL2 features rather than
  relying on its nMASK (Joey)
- Add new system registers to the auto-generated sysreg rather
  than hardcoding them (Mark)
- Drop patch that was meant as RFC
- Added missing system registers, fields, and  system
  instructions
- Split patches that make system register changes
- Fixes to patches defining allowed features for protected VMs
- Other minor fixes and tidying up

Changes from v1:
- Handle HAFGRTR_EL2 in nested virt
- Update the nested virt FGT tables with the added trap bits (Marc)
- Use the generated value for RES0 (Marc)
- Calculate the value of NMASK based on RES0 and MASK

This patch series has fixes, updates, and code for validating
fine grain trap register masks, as well as some fixes to feature
trapping in pKVM.

New fine grain trap (FGT) bits have been defined in the latest
Arm Architecture System Registers xml specification (DDI0601 and
DDI0602 2023-09) [1], so the code is updated to reflect them.
Moreover, some of the already-defined masks overlap with RES0,
which this series fixes.

It also adds FGT register masks that weren't defined earlier,
handling of HAFGRTR_EL2 in nested virt, as well as build time
validation that the bits of the various masks are all accounted
for and without overlap.

Based on arm64/for-next/sysregs (e94e06d8a796), which is composed
of system register updates [2] and is based on Linux 6.7-rc3.

Cheers,
/fuad

[1] https://developer.arm.com/downloads/-/exploration-tools
[2] https://lore.kernel.org/all/20231209-b4-arm64-sysreg-additions-v1-0-45284e538474@kernel.org/

Fuad Tabba (17):
  arm64/sysreg: Add missing Pauth_LR field definitions to
    ID_AA64ISAR1_EL1
  arm64/sysreg: Add missing ExtTrcBuff field definition to
    ID_AA64DFR0_EL1
  arm64/sysreg: Add missing system register definitions for FGT
  arm64/sysreg: Add missing system instruction definitions for FGT
  KVM: arm64: Explicitly trap unsupported HFGxTR_EL2 features
  KVM: arm64: Add missing HFGxTR_EL2 FGT entries to nested virt
  KVM: arm64: Add missing HFGITR_EL2 FGT entries to nested virt
  KVM: arm64: Add bit masks for HAFGRTR_EL2
  KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt
  KVM: arm64: Update and fix FGT register masks
  KVM: arm64: Add build validation for FGT trap mask values
  KVM: arm64: Use generated FGT RES0 bits instead of specifying them
  KVM: arm64: Define FGT nMASK bits relative to other fields
  KVM: arm64: Macros for setting/clearing FGT bits
  KVM: arm64: Fix which features are marked as allowed for protected VMs
  KVM: arm64: Mark PAuth as a restricted feature for protected VMs
  KVM: arm64: Trap external trace for protected VMs

 arch/arm64/include/asm/kvm_arm.h              | 61 +++++++++------
 arch/arm64/include/asm/kvm_host.h             |  1 +
 arch/arm64/include/asm/sysreg.h               |  7 ++
 arch/arm64/kvm/emulate-nested.c               | 63 +++++++++++++++
 arch/arm64/kvm/hyp/include/hyp/switch.h       | 77 +++++++++++--------
 .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 22 +++++-
 arch/arm64/kvm/hyp/nvhe/pkvm.c                |  4 +
 arch/arm64/kvm/sys_regs.c                     |  1 +
 arch/arm64/tools/sysreg                       | 50 +++++++++++-
 9 files changed, 225 insertions(+), 61 deletions(-)


base-commit: e94e06d8a7960fd840ea92021ca1bf1362ea67f8
-- 
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[PATCH v3 01/17] arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1

[Fuad Tabba]

Add the Pauth_LR field definitions to ID_AA64ISAR1_EL1, based on
DDI0601 2023-09.

These fields aren't used yet. Adding them for completeness and
consistency (definition already exists for ID_AA64ISAR2_EL1).

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/tools/sysreg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 2c4b6665c5bf..d596be2599d1 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1401,6 +1401,7 @@ UnsignedEnum	11:8	API
 	0b0011	PAuth2
 	0b0100	FPAC
 	0b0101	FPACCOMBINE
+	0b0110	PAuth_LR
 EndEnum
 UnsignedEnum	7:4	APA
 	0b0000	NI
@@ -1409,6 +1410,7 @@ UnsignedEnum	7:4	APA
 	0b0011	PAuth2
 	0b0100	FPAC
 	0b0101	FPACCOMBINE
+	0b0110	PAuth_LR
 EndEnum
 UnsignedEnum	3:0	DPB
 	0b0000	NI
-- 
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[PATCH v3 02/17] arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1

[Fuad Tabba]

Add the ExtTrcBuff field definitions to ID_AA64DFR0_EL1 from
DDI0601 2023-09.

This field isn't used yet. Adding it for completeness and because
it will be used in future patches.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/tools/sysreg | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index d596be2599d1..a8e36640c027 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1189,7 +1189,10 @@ Enum	63:60	HPMN0
 	0b0000	UNPREDICTABLE
 	0b0001	DEF
 EndEnum
-Res0	59:56
+UnsignedEnum	59:56	ExtTrcBuff
+	0b0000	NI
+	0b0001	IMP
+EndEnum
 UnsignedEnum	55:52	BRBE
 	0b0000	NI
 	0b0001	IMP
-- 
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[PATCH v3 03/17] arm64/sysreg: Add missing system register definitions for FGT

[Fuad Tabba]

Add the definitions of missing system registers that are
trappable by fine grain traps. The definitions are based on
DDI0601 2023-09.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/tools/sysreg | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a8e36640c027..5ceaa1d3630e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2086,10 +2086,18 @@ Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
 Fields	CONTEXTIDR_ELx
 EndSysreg
 
+Sysreg	RCWSMASK_EL1	3	0	13	0	3
+Field	63:0	RCWSMASK
+EndSysreg
+
 Sysreg	TPIDR_EL1	3	0	13	0	4
 Field	63:0	ThreadID
 EndSysreg
 
+Sysreg	RCWMASK_EL1	3	0	13	0	6
+Field	63:0	RCWMASK
+EndSysreg
+
 Sysreg	SCXTNUM_EL1	3	0	13	0	7
 Field	63:0	SoftwareContextNumber
 EndSysreg
@@ -2714,6 +2722,33 @@ Field	1	PIE
 Field	0	PnCH
 EndSysreg
 
+SysregFields MAIR2_ELx
+Field	63:56	Attr7
+Field	55:48	Attr6
+Field	47:40	Attr5
+Field	39:32	Attr4
+Field	31:24	Attr3
+Field	23:16	Attr2
+Field	15:8	Attr1
+Field	7:0	Attr0
+EndSysregFields
+
+Sysreg	MAIR2_EL1	3	0	10	2	1
+Fields	MAIR2_ELx
+EndSysreg
+
+Sysreg	MAIR2_EL2	3	4	10	1	1
+Fields	MAIR2_ELx
+EndSysreg
+
+Sysreg	AMAIR2_EL1	3	0	10	3	1
+Field	63:0	ImpDef
+EndSysreg
+
+Sysreg	AMAIR2_EL2	3	4	10	3	1
+Field	63:0	ImpDef
+EndSysreg
+
 SysregFields PIRx_ELx
 Field	63:60	Perm15
 Field	59:56	Perm14
@@ -2765,6 +2800,14 @@ Sysreg	POR_EL12	3	5	10	2	4
 Fields	PIRx_ELx
 EndSysreg
 
+Sysreg	S2POR_EL1	3	0	10	2	5
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	S2PIR_EL2	3	4	10	2	5
+Fields	PIRx_ELx
+EndSysreg
+
 Sysreg	LORSA_EL1	3	0	10	4	0
 Res0	63:52
 Field	51:16	SA
-- 
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[PATCH v3 04/17] arm64/sysreg: Add missing system instruction definitions for FGT

[Fuad Tabba]

Add the definitions of missing system instructions that are
trappable by fine grain traps. The definitions are based on
DDI0602 2023-09.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/sysreg.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9c2caf0efdc7..b320fb0de56b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -645,6 +645,7 @@
 #define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
 #define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
 #define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
+#define OP_AT_S1E1A	sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
 #define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
 #define OP_AT_S1E2W	sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
 #define OP_AT_S12E1R	sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
@@ -781,10 +782,16 @@
 #define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
 
 /* Misc instructions */
+#define OP_GCSPUSHX			sys_insn(1, 0, 7, 7, 4)
+#define OP_GCSPOPCX			sys_insn(1, 0, 7, 7, 5)
+#define OP_GCSPOPX			sys_insn(1, 0, 7, 7, 6)
+#define OP_GCSPUSHM			sys_insn(1, 3, 7, 7, 0)
+
 #define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
 #define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
 #define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
 #define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
+#define OP_COSP_RCTX			sys_insn(1, 3, 7, 3, 6)
 #define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
 
 /* Common SCTLR_ELx flags. */
-- 
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[PATCH v3 05/17] KVM: arm64: Explicitly trap unsupported HFGxTR_EL2 features

[Fuad Tabba]

Do not rely on the value of __HFGRTR_EL2_nMASK to trap
unsupported features, since the nMASK can (and will) change as
new traps are added and as its value is updated. Instead,
explicitly specify the trap bits.

Suggested-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/include/hyp/switch.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index f99d8af0b9af..7b4909dfd1f5 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -110,12 +110,15 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 		compute_clr_set(vcpu, HFGWTR_EL2, w_clr, w_set);
 	}
 
-	/* The default is not to trap anything but ACCDATA_EL1 */
-	r_val = __HFGRTR_EL2_nMASK & ~HFGxTR_EL2_nACCDATA_EL1;
+	/* The default to trap everything not handled or supported in KVM. */
+	tmp = HFGxTR_EL2_nAMAIR2_EL1 | HFGxTR_EL2_nMAIR2_EL1 | HFGxTR_EL2_nS2POR_EL1 |
+	      HFGxTR_EL2_nPOR_EL1 | HFGxTR_EL2_nPOR_EL0 | HFGxTR_EL2_nACCDATA_EL1;
+
+	r_val = __HFGRTR_EL2_nMASK & ~tmp;
 	r_val |= r_set;
 	r_val &= ~r_clr;
 
-	w_val = __HFGWTR_EL2_nMASK & ~HFGxTR_EL2_nACCDATA_EL1;
+	w_val = __HFGWTR_EL2_nMASK & ~tmp;
 	w_val |= w_set;
 	w_val &= ~w_clr;
 
-- 
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[PATCH v3 06/17] KVM: arm64: Add missing HFGxTR_EL2 FGT entries to nested virt

[Fuad Tabba]

Add the missing nested virt FGT table entries HFGxTR_EL2. Based
on DDI0601 2023-09.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/emulate-nested.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 06185216a297..8b473a1bbc11 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1042,10 +1042,20 @@ enum fg_filter_id {
 
 static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
 	/* HFGRTR_EL2, HFGWTR_EL2 */
+	SR_FGT(SYS_AMAIR2_EL1,		HFGxTR, nAMAIR2_EL1, 0),
+	SR_FGT(SYS_MAIR2_EL1,		HFGxTR, nMAIR2_EL1, 0),
+	SR_FGT(SYS_S2POR_EL1,		HFGxTR, nS2POR_EL1, 0),
+	SR_FGT(SYS_POR_EL1,		HFGxTR, nPOR_EL1, 0),
+	SR_FGT(SYS_POR_EL0,		HFGxTR, nPOR_EL0, 0),
 	SR_FGT(SYS_PIR_EL1,		HFGxTR, nPIR_EL1, 0),
 	SR_FGT(SYS_PIRE0_EL1,		HFGxTR, nPIRE0_EL1, 0),
+	SR_FGT(SYS_RCWMASK_EL1,		HFGxTR, nRCWMASK_EL1, 0),
 	SR_FGT(SYS_TPIDR2_EL0,		HFGxTR, nTPIDR2_EL0, 0),
 	SR_FGT(SYS_SMPRI_EL1,		HFGxTR, nSMPRI_EL1, 0),
+	SR_FGT(SYS_GCSCR_EL1,		HFGxTR, nGCS_EL1, 0),
+	SR_FGT(SYS_GCSPR_EL1,		HFGxTR, nGCS_EL1, 0),
+	SR_FGT(SYS_GCSCRE0_EL1,		HFGxTR, nGCS_EL0, 0),
+	SR_FGT(SYS_GCSPR_EL0,		HFGxTR, nGCS_EL0, 0),
 	SR_FGT(SYS_ACCDATA_EL1,		HFGxTR, nACCDATA_EL1, 0),
 	SR_FGT(SYS_ERXADDR_EL1,		HFGxTR, ERXADDR_EL1, 1),
 	SR_FGT(SYS_ERXPFGCDN_EL1,	HFGxTR, ERXPFGCDN_EL1, 1),
-- 
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[PATCH v3 07/17] KVM: arm64: Add missing HFGITR_EL2 FGT entries to nested virt

[Fuad Tabba]

Add the missing nested virt FGT table entries HFGITR_EL2. Based
on DDI0601 and DDI0602 2023-09.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/emulate-nested.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 8b473a1bbc11..89901550db34 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1117,6 +1117,11 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
 	SR_FGT(SYS_AFSR1_EL1, 		HFGxTR, AFSR1_EL1, 1),
 	SR_FGT(SYS_AFSR0_EL1, 		HFGxTR, AFSR0_EL1, 1),
 	/* HFGITR_EL2 */
+	SR_FGT(OP_AT_S1E1A, 		HFGITR, ATS1E1A, 1),
+	SR_FGT(OP_COSP_RCTX, 		HFGITR, COSPRCTX, 1),
+	SR_FGT(OP_GCSPUSHX, 		HFGITR, nGCSEPP, 0),
+	SR_FGT(OP_GCSPOPX, 		HFGITR, nGCSEPP, 0),
+	SR_FGT(OP_GCSPUSHM, 		HFGITR, nGCSPUSHM_EL1, 0),
 	SR_FGT(OP_BRB_IALL, 		HFGITR, nBRBIALL, 0),
 	SR_FGT(OP_BRB_INJ, 		HFGITR, nBRBINJ, 0),
 	SR_FGT(SYS_DC_CVAC, 		HFGITR, DCCVAC, 1),
-- 
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[PATCH v3 08/17] KVM: arm64: Add bit masks for HAFGRTR_EL2

[Fuad Tabba]

To support HAFGRTR_EL2 supported in nested virt in the following
patch, first add its bitmask definitions based on DDI0601 2023-09.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b85f46a73e21..7de0a7062625 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -370,6 +370,10 @@
 #define __HDFGWTR_EL2_MASK	~__HDFGWTR_EL2_nMASK
 #define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
 
+#define __HAFGRTR_EL2_RES0	(GENMASK(63, 50) | GENMASK(16, 5))
+#define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
+#define __HAFGRTR_EL2_nMASK	0UL
+
 /* Similar definitions for HCRX_EL2 */
 #define __HCRX_EL2_RES0		(GENMASK(63, 16) | GENMASK(13, 12))
 #define __HCRX_EL2_MASK		(0)
-- 
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[PATCH v3 09/17] KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt

[Fuad Tabba]

Add the encodings to fine grain trapping fields for HAFGRTR_EL2
and add the associated handling code in nested virt. Based on
DDI0601 2023-09. Add the missing field definitions as well,
both to generate the correct RES0 mask and to be able to toggle
their FGT bits.

Also add the code for handling FGT trapping, reading of the
register, to nested virt.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_host.h       |  1 +
 arch/arm64/kvm/emulate-nested.c         | 48 +++++++++++++++++++++++++
 arch/arm64/kvm/hyp/include/hyp/switch.h | 12 +++++++
 arch/arm64/kvm/sys_regs.c               |  1 +
 4 files changed, 62 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 824f29f04916..ba14648e2de2 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -443,6 +443,7 @@ enum vcpu_sysreg {
 	HFGITR_EL2,
 	HDFGRTR_EL2,
 	HDFGWTR_EL2,
+	HAFGRTR_EL2,
 	CNTHP_CTL_EL2,
 	CNTHP_CVAL_EL2,
 	CNTHV_CTL_EL2,
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 89901550db34..431fd429932d 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1012,6 +1012,7 @@ enum fgt_group_id {
 	HDFGRTR_GROUP,
 	HDFGWTR_GROUP,
 	HFGITR_GROUP,
+	HAFGRTR_GROUP,
 
 	/* Must be last */
 	__NR_FGT_GROUP_IDS__
@@ -1689,6 +1690,49 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
 	SR_FGT(SYS_PMCR_EL0,		HDFGWTR, PMCR_EL0, 1),
 	SR_FGT(SYS_PMSWINC_EL0,		HDFGWTR, PMSWINC_EL0, 1),
 	SR_FGT(SYS_OSLAR_EL1,		HDFGWTR, OSLAR_EL1, 1),
+	/*
+	 * HAFGRTR_EL2
+	 */
+	SR_FGT(SYS_AMEVTYPER1_EL0(15),	HAFGRTR, AMEVTYPER115_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(14),	HAFGRTR, AMEVTYPER114_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(13),	HAFGRTR, AMEVTYPER113_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(12),	HAFGRTR, AMEVTYPER112_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(11),	HAFGRTR, AMEVTYPER111_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(10),	HAFGRTR, AMEVTYPER110_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(9),	HAFGRTR, AMEVTYPER19_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(8),	HAFGRTR, AMEVTYPER18_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(7),	HAFGRTR, AMEVTYPER17_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(6),	HAFGRTR, AMEVTYPER16_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(5),	HAFGRTR, AMEVTYPER15_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(4),	HAFGRTR, AMEVTYPER14_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(3),	HAFGRTR, AMEVTYPER13_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(2),	HAFGRTR, AMEVTYPER12_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(1),	HAFGRTR, AMEVTYPER11_EL0, 1),
+	SR_FGT(SYS_AMEVTYPER1_EL0(0),	HAFGRTR, AMEVTYPER10_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(15),	HAFGRTR, AMEVCNTR115_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(14),	HAFGRTR, AMEVCNTR114_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(13),	HAFGRTR, AMEVCNTR113_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(12),	HAFGRTR, AMEVCNTR112_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(11),	HAFGRTR, AMEVCNTR111_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(10),	HAFGRTR, AMEVCNTR110_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(9),	HAFGRTR, AMEVCNTR19_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(8),	HAFGRTR, AMEVCNTR18_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(7),	HAFGRTR, AMEVCNTR17_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(6),	HAFGRTR, AMEVCNTR16_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(5),	HAFGRTR, AMEVCNTR15_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(4),	HAFGRTR, AMEVCNTR14_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(3),	HAFGRTR, AMEVCNTR13_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(2),	HAFGRTR, AMEVCNTR12_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(1),	HAFGRTR, AMEVCNTR11_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR1_EL0(0),	HAFGRTR, AMEVCNTR10_EL0, 1),
+	SR_FGT(SYS_AMCNTENCLR1_EL0,	HAFGRTR, AMCNTEN1, 1),
+	SR_FGT(SYS_AMCNTENSET1_EL0,	HAFGRTR, AMCNTEN1, 1),
+	SR_FGT(SYS_AMCNTENCLR0_EL0,	HAFGRTR, AMCNTEN0, 1),
+	SR_FGT(SYS_AMCNTENSET0_EL0,	HAFGRTR, AMCNTEN0, 1),
+	SR_FGT(SYS_AMEVCNTR0_EL0(3),	HAFGRTR, AMEVCNTR03_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR0_EL0(2),	HAFGRTR, AMEVCNTR02_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR0_EL0(1),	HAFGRTR, AMEVCNTR01_EL0, 1),
+	SR_FGT(SYS_AMEVCNTR0_EL0(0),	HAFGRTR, AMEVCNTR00_EL0, 1),
 };
 
 static union trap_config get_trap_config(u32 sysreg)
@@ -1909,6 +1953,10 @@ bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
 			val = sanitised_sys_reg(vcpu, HDFGWTR_EL2);
 		break;
 
+	case HAFGRTR_GROUP:
+		val = sanitised_sys_reg(vcpu, HAFGRTR_EL2);
+		break;
+
 	case HFGITR_GROUP:
 		val = sanitised_sys_reg(vcpu, HFGITR_EL2);
 		switch (tc.fgf) {
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 7b4909dfd1f5..22f3b916f60c 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -156,6 +156,17 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 
 	write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
 	write_sysreg_s(w_val, SYS_HDFGWTR_EL2);
+
+	ctxt_sys_reg(hctxt, HAFGRTR_EL2) = read_sysreg_s(SYS_HAFGRTR_EL2);
+
+	r_clr = r_set = 0;
+	compute_clr_set(vcpu, HAFGRTR_EL2, r_clr, r_set);
+
+	r_val = __HAFGRTR_EL2_nMASK;
+	r_val |= r_set;
+	r_val &= ~r_clr;
+
+	write_sysreg_s(r_val, SYS_HAFGRTR_EL2);
 }
 
 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
@@ -174,6 +185,7 @@ static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 	write_sysreg_s(ctxt_sys_reg(hctxt, HFGITR_EL2), SYS_HFGITR_EL2);
 	write_sysreg_s(ctxt_sys_reg(hctxt, HDFGRTR_EL2), SYS_HDFGRTR_EL2);
 	write_sysreg_s(ctxt_sys_reg(hctxt, HDFGWTR_EL2), SYS_HDFGWTR_EL2);
+	write_sysreg_s(ctxt_sys_reg(hctxt, HAFGRTR_EL2), SYS_HAFGRTR_EL2);
 }
 
 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 4735e1b37fb3..8bb297a2df38 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2532,6 +2532,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
 	EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
 	EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
+	EL2_REG(HAFGRTR_EL2, access_rw, reset_val, 0),
 	EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
 	EL2_REG(ELR_EL2, access_rw, reset_val, 0),
 	{ SYS_DESC(SYS_SP_EL1), access_sp_el1},
-- 
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[PATCH v3 10/17] KVM: arm64: Update and fix FGT register masks

[Fuad Tabba]

New trap bits have been defined since the latest update to this
patch.  Moreover, the existing definitions of some of the mask
and the RES0 bits overlap, which could be wrong, confusing, or
both.

Update the bits based on DDI0601 2023-09, and ensure that the
existing bits are consistent.

Subsequent patches will use the generated RES0 fields instead of
specifying them manually. This patch keeps the manual encoding of
the bits to make it easier to review the series.

Fixes: 0fd76865006d ("KVM: arm64: Add nPIR{E0}_EL1 to HFG traps")
Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 39 ++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 7de0a7062625..b0dc3249d5cd 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -344,30 +344,39 @@
  * Once we get to a point where the two describe the same thing, we'll
  * merge the definitions. One day.
  */
-#define __HFGRTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51))
+#define __HFGRTR_EL2_RES0	BIT(51)
 #define __HFGRTR_EL2_MASK	GENMASK(49, 0)
-#define __HFGRTR_EL2_nMASK	(GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
+#define __HFGRTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
 
-#define __HFGWTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51) |	\
-				 BIT(46) | BIT(42) | BIT(40) | BIT(28) | \
-				 GENMASK(26, 25) | BIT(21) | BIT(18) |	\
+#define __HFGWTR_EL2_RES0	(BIT(51) | BIT(46) | BIT(42) | BIT(40) | \
+				 BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \
 				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
-#define __HFGWTR_EL2_MASK	GENMASK(49, 0)
-#define __HFGWTR_EL2_nMASK	(GENMASK(58, 57) | GENMASK(55, 54) | BIT(50))
+#define __HFGWTR_EL2_MASK	(GENMASK(49, 47) | GENMASK(45, 43) | \
+				 BIT(41) | GENMASK(39, 29) | BIT(27) | \
+				 GENMASK(24, 22) | GENMASK(20, 19) | \
+				 GENMASK(17, 16) | GENMASK(13, 11) | \
+				 GENMASK(8, 3) | GENMASK(1, 0))
+#define __HFGWTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
 
-#define __HFGITR_EL2_RES0	GENMASK(63, 57)
-#define __HFGITR_EL2_MASK	GENMASK(54, 0)
-#define __HFGITR_EL2_nMASK	GENMASK(56, 55)
+#define __HFGITR_EL2_RES0	(BIT(63) | BIT(61))
+#define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
+#define __HFGITR_EL2_nMASK	GENMASK(59, 55)
 
 #define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\
 				 GENMASK(21, 20) | BIT(8))
-#define __HDFGRTR_EL2_MASK	~__HDFGRTR_EL2_nMASK
+#define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
+				 GENMASK(41, 40) | GENMASK(37, 22) | \
+				 GENMASK(19, 9) | GENMASK(7, 0))
 #define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)
 
 #define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \
 				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \
 				 BIT(22) | BIT(9) | BIT(6))
-#define __HDFGWTR_EL2_MASK	~__HDFGWTR_EL2_nMASK
+#define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
+				 GENMASK(46, 44) | GENMASK(42, 41) | \
+				 GENMASK(37, 35) | GENMASK(33, 31) | \
+				 GENMASK(29, 23) | GENMASK(21, 10) | \
+				 GENMASK(8, 7) | GENMASK(5, 0))
 #define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
 
 #define __HAFGRTR_EL2_RES0	(GENMASK(63, 50) | GENMASK(16, 5))
@@ -375,9 +384,9 @@
 #define __HAFGRTR_EL2_nMASK	0UL
 
 /* Similar definitions for HCRX_EL2 */
-#define __HCRX_EL2_RES0		(GENMASK(63, 16) | GENMASK(13, 12))
-#define __HCRX_EL2_MASK		(0)
-#define __HCRX_EL2_nMASK	(GENMASK(15, 14) | GENMASK(4, 0))
+#define __HCRX_EL2_RES0         (GENMASK(63, 25) | GENMASK(13, 12))
+#define __HCRX_EL2_MASK		(BIT(6))
+#define __HCRX_EL2_nMASK	(GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
 
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 #define HPFAR_MASK	(~UL(0xf))
-- 
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[PATCH v3 11/17] KVM: arm64: Add build validation for FGT trap mask values

[Fuad Tabba]

These checks help ensure that all the bits are accounted for,
that there hasn't been a transcribing error from the spec nor
from the generated mask values, which will be used in subsequent
patches.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/include/hyp/switch.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 22f3b916f60c..17ce40f5b006 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -79,6 +79,16 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 		clr |= ~hfg & __ ## reg ## _nMASK; 			\
 	} while(0)
 
+/*
+ * Validate the fine grain trap masks.
+ * Check that the masks do not overlap and that all bits are accounted for.
+ */
+#define CHECK_FGT_MASKS(reg)							\
+	do {									\
+		BUILD_BUG_ON((__ ## reg ## _MASK) & (__ ## reg ## _nMASK));	\
+		BUILD_BUG_ON(~((__ ## reg ## _RES0) ^ (__ ## reg ## _MASK) ^	\
+			       (__ ## reg ## _nMASK)));				\
+	} while(0)
 
 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 {
@@ -86,6 +96,14 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 	u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
 	u64 r_val, w_val;
 
+	CHECK_FGT_MASKS(HFGRTR_EL2);
+	CHECK_FGT_MASKS(HFGWTR_EL2);
+	CHECK_FGT_MASKS(HFGITR_EL2);
+	CHECK_FGT_MASKS(HDFGRTR_EL2);
+	CHECK_FGT_MASKS(HDFGWTR_EL2);
+	CHECK_FGT_MASKS(HAFGRTR_EL2);
+	CHECK_FGT_MASKS(HCRX_EL2);
+
 	if (!cpus_have_final_cap(ARM64_HAS_FGT))
 		return;
 
-- 
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[PATCH v3 12/17] KVM: arm64: Use generated FGT RES0 bits instead of specifying them

[Fuad Tabba]

Now that all FGT fields are accounted for and represented, use
the generated value instead of manually specifying them.

For __HFGWTR_EL2_RES0, however, there is no generated value. Its
fields are subset of HFGRTR_EL2, with the remaining being RES0.
Therefore, add a mask that represents the HFGRTR_EL2 only bits
and define __HFGWTR_EL2_* using those and the __HFGRTR_EL2_*
fields.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 34 +++++++++++++++-----------------
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b0dc3249d5cd..bd20d27f1b33 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -344,34 +344,32 @@
  * Once we get to a point where the two describe the same thing, we'll
  * merge the definitions. One day.
  */
-#define __HFGRTR_EL2_RES0	BIT(51)
+#define __HFGRTR_EL2_RES0	HFGxTR_EL2_RES0
 #define __HFGRTR_EL2_MASK	GENMASK(49, 0)
 #define __HFGRTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
 
-#define __HFGWTR_EL2_RES0	(BIT(51) | BIT(46) | BIT(42) | BIT(40) | \
-				 BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \
+/*
+ * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any
+ * future additions, define __HFGWTR* macros relative to __HFGRTR* ones.
+ */
+#define __HFGRTR_ONLY_MASK	(BIT(46) | BIT(42) | BIT(40) | BIT(28) | \
+				 GENMASK(26, 25) | BIT(21) | BIT(18) | \
 				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
-#define __HFGWTR_EL2_MASK	(GENMASK(49, 47) | GENMASK(45, 43) | \
-				 BIT(41) | GENMASK(39, 29) | BIT(27) | \
-				 GENMASK(24, 22) | GENMASK(20, 19) | \
-				 GENMASK(17, 16) | GENMASK(13, 11) | \
-				 GENMASK(8, 3) | GENMASK(1, 0))
-#define __HFGWTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
-
-#define __HFGITR_EL2_RES0	(BIT(63) | BIT(61))
+#define __HFGWTR_EL2_RES0	(__HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK)
+#define __HFGWTR_EL2_MASK	(__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)
+#define __HFGWTR_EL2_nMASK	(__HFGRTR_EL2_nMASK & ~__HFGRTR_ONLY_MASK)
+
+#define __HFGITR_EL2_RES0	HFGITR_EL2_RES0
 #define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
 #define __HFGITR_EL2_nMASK	GENMASK(59, 55)
 
-#define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\
-				 GENMASK(21, 20) | BIT(8))
+#define __HDFGRTR_EL2_RES0	HDFGRTR_EL2_RES0
 #define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
 				 GENMASK(41, 40) | GENMASK(37, 22) | \
 				 GENMASK(19, 9) | GENMASK(7, 0))
 #define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)
 
-#define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \
-				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \
-				 BIT(22) | BIT(9) | BIT(6))
+#define __HDFGWTR_EL2_RES0	HDFGWTR_EL2_RES0
 #define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
 				 GENMASK(46, 44) | GENMASK(42, 41) | \
 				 GENMASK(37, 35) | GENMASK(33, 31) | \
@@ -379,12 +377,12 @@
 				 GENMASK(8, 7) | GENMASK(5, 0))
 #define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
 
-#define __HAFGRTR_EL2_RES0	(GENMASK(63, 50) | GENMASK(16, 5))
+#define __HAFGRTR_EL2_RES0	HAFGRTR_EL2_RES0
 #define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
 #define __HAFGRTR_EL2_nMASK	0UL
 
 /* Similar definitions for HCRX_EL2 */
-#define __HCRX_EL2_RES0         (GENMASK(63, 25) | GENMASK(13, 12))
+#define __HCRX_EL2_RES0         HCRX_EL2_RES0
 #define __HCRX_EL2_MASK		(BIT(6))
 #define __HCRX_EL2_nMASK	(GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
 
-- 
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[PATCH v3 13/17] KVM: arm64: Define FGT nMASK bits relative to other fields

[Fuad Tabba]

Now that RES0 and MASK have full coverage, no speed to manually
encode nMASK. Calculate it relative to the other fields.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index bd20d27f1b33..b7a9fe36bb59 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -346,7 +346,7 @@
  */
 #define __HFGRTR_EL2_RES0	HFGxTR_EL2_RES0
 #define __HFGRTR_EL2_MASK	GENMASK(49, 0)
-#define __HFGRTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
+#define __HFGRTR_EL2_nMASK	~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK)
 
 /*
  * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any
@@ -357,17 +357,17 @@
 				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
 #define __HFGWTR_EL2_RES0	(__HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK)
 #define __HFGWTR_EL2_MASK	(__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)
-#define __HFGWTR_EL2_nMASK	(__HFGRTR_EL2_nMASK & ~__HFGRTR_ONLY_MASK)
+#define __HFGWTR_EL2_nMASK	~(__HFGWTR_EL2_RES0 | __HFGWTR_EL2_MASK)
 
 #define __HFGITR_EL2_RES0	HFGITR_EL2_RES0
 #define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
-#define __HFGITR_EL2_nMASK	GENMASK(59, 55)
+#define __HFGITR_EL2_nMASK	~(__HFGITR_EL2_RES0 | __HFGITR_EL2_MASK)
 
 #define __HDFGRTR_EL2_RES0	HDFGRTR_EL2_RES0
 #define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
 				 GENMASK(41, 40) | GENMASK(37, 22) | \
 				 GENMASK(19, 9) | GENMASK(7, 0))
-#define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)
+#define __HDFGRTR_EL2_nMASK	~(__HDFGRTR_EL2_RES0 | __HDFGRTR_EL2_MASK)
 
 #define __HDFGWTR_EL2_RES0	HDFGWTR_EL2_RES0
 #define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
@@ -375,16 +375,16 @@
 				 GENMASK(37, 35) | GENMASK(33, 31) | \
 				 GENMASK(29, 23) | GENMASK(21, 10) | \
 				 GENMASK(8, 7) | GENMASK(5, 0))
-#define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
+#define __HDFGWTR_EL2_nMASK	~(__HDFGWTR_EL2_RES0 | __HDFGWTR_EL2_MASK)
 
 #define __HAFGRTR_EL2_RES0	HAFGRTR_EL2_RES0
 #define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
-#define __HAFGRTR_EL2_nMASK	0UL
+#define __HAFGRTR_EL2_nMASK	~(__HAFGRTR_EL2_RES0 | __HAFGRTR_EL2_MASK)
 
 /* Similar definitions for HCRX_EL2 */
 #define __HCRX_EL2_RES0         HCRX_EL2_RES0
 #define __HCRX_EL2_MASK		(BIT(6))
-#define __HCRX_EL2_nMASK	(GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
+#define __HCRX_EL2_nMASK	~(__HCRX_EL2_RES0 | __HCRX_EL2_MASK)
 
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 #define HPFAR_MASK	(~UL(0xf))
-- 
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[PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Fuad Tabba]

There's a lot of boilerplate code for setting and clearing FGT
bits when activating guest traps. Refactor it into macros. These
macros will also be used in future patch series.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++----------------
 1 file changed, 21 insertions(+), 39 deletions(-)

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 17ce40f5b006..e223fc0d5193 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 		clr |= ~hfg & __ ## reg ## _nMASK; 			\
 	} while(0)
 
+#define update_fgt_traps_cs(reg, clr, set)				\
+	do {								\
+		struct kvm_cpu_context *hctxt =				\
+			&this_cpu_ptr(&kvm_host_data)->host_ctxt;	\
+		u64 val, c = 0, s = 0;					\
+									\
+		ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);	\
+		compute_clr_set(vcpu, reg, c, s);			\
+		val = __ ## reg ## _nMASK;				\
+		val |= (s | set);					\
+		val &= ~(c | clr);					\
+		write_sysreg_s(val, SYS_ ## reg);			\
+	} while(0)
+
+#define update_fgt_traps(reg)						\
+	update_fgt_traps_cs(reg, 0, 0)
+
 /*
  * Validate the fine grain trap masks.
  * Check that the masks do not overlap and that all bits are accounted for.
@@ -146,45 +163,10 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 	if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
 		return;
 
-	ctxt_sys_reg(hctxt, HFGITR_EL2) = read_sysreg_s(SYS_HFGITR_EL2);
-
-	r_set = r_clr = 0;
-	compute_clr_set(vcpu, HFGITR_EL2, r_clr, r_set);
-	r_val = __HFGITR_EL2_nMASK;
-	r_val |= r_set;
-	r_val &= ~r_clr;
-
-	write_sysreg_s(r_val, SYS_HFGITR_EL2);
-
-	ctxt_sys_reg(hctxt, HDFGRTR_EL2) = read_sysreg_s(SYS_HDFGRTR_EL2);
-	ctxt_sys_reg(hctxt, HDFGWTR_EL2) = read_sysreg_s(SYS_HDFGWTR_EL2);
-
-	r_clr = r_set = w_clr = w_set = 0;
-
-	compute_clr_set(vcpu, HDFGRTR_EL2, r_clr, r_set);
-	compute_clr_set(vcpu, HDFGWTR_EL2, w_clr, w_set);
-
-	r_val = __HDFGRTR_EL2_nMASK;
-	r_val |= r_set;
-	r_val &= ~r_clr;
-
-	w_val = __HDFGWTR_EL2_nMASK;
-	w_val |= w_set;
-	w_val &= ~w_clr;
-
-	write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
-	write_sysreg_s(w_val, SYS_HDFGWTR_EL2);
-
-	ctxt_sys_reg(hctxt, HAFGRTR_EL2) = read_sysreg_s(SYS_HAFGRTR_EL2);
-
-	r_clr = r_set = 0;
-	compute_clr_set(vcpu, HAFGRTR_EL2, r_clr, r_set);
-
-	r_val = __HAFGRTR_EL2_nMASK;
-	r_val |= r_set;
-	r_val &= ~r_clr;
-
-	write_sysreg_s(r_val, SYS_HAFGRTR_EL2);
+	update_fgt_traps(HFGITR_EL2);
+	update_fgt_traps(HDFGRTR_EL2);
+	update_fgt_traps(HDFGWTR_EL2);
+	update_fgt_traps(HAFGRTR_EL2);
 }
 
 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
-- 
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[PATCH v3 15/17] KVM: arm64: Fix which features are marked as allowed for protected VMs

[Fuad Tabba]

Cache maintenance operations are not trapped for protected VMs,
and shouldn't be. Mark them as allowed.

Moreover, features advertised by ID_AA64PFR2 and ID_AA64MMFR3 are
(already) not allowed, mark them as such.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index e91922daa8ca..8d97dff4bb7b 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -69,6 +69,8 @@
 	ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \
 	)
 
+#define PVM_ID_AA64PFR2_ALLOW 0ULL
+
 /*
  * Allow for protected VMs:
  * - Mixed-endian
@@ -101,6 +103,7 @@
  * - Privileged Access Never
  * - SError interrupt exceptions from speculative reads
  * - Enhanced Translation Synchronization
+ * - Control for cache maintenance permission
  */
 #define PVM_ID_AA64MMFR1_ALLOW (\
 	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
@@ -108,7 +111,8 @@
 	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
 	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
 	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_CMOW) \
 	)
 
 /*
@@ -133,6 +137,8 @@
 	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \
 	)
 
+#define PVM_ID_AA64MMFR3_ALLOW (0ULL)
+
 /*
  * No support for Scalable Vectors for protected VMs:
  *	Requires additional support from KVM, e.g., context-switching and
-- 
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[PATCH v3 16/17] KVM: arm64: Mark PAuth as a restricted feature for protected VMs

[Fuad Tabba]

Protected VMs will only support basic PAuth (FEAT_PAuth). Mark it
as restricted to ensure that later versions aren't supported for
protected guests.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 8d97dff4bb7b..51f043649146 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -184,10 +184,18 @@
 	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \
 	)
 
+/* Restrict pointer authentication to the basic version. */
+#define PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED (\
+	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), ID_AA64ISAR1_EL1_APA_PAuth) | \
+	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), ID_AA64ISAR1_EL1_API_PAuth) \
+	)
+
+#define PVM_ID_AA64ISAR2_RESTRICT_UNSIGNED (\
+	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3), ID_AA64ISAR2_EL1_APA3_PAuth) \
+	)
+
 #define PVM_ID_AA64ISAR1_ALLOW (\
 	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \
-	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \
-	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \
 	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \
 	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \
 	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \
@@ -202,8 +210,8 @@
 	)
 
 #define PVM_ID_AA64ISAR2_ALLOW (\
+	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_ATS1A)| \
 	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
-	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | \
 	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS) \
 	)
 
-- 
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[PATCH v3 17/17] KVM: arm64: Trap external trace for protected VMs

[Fuad Tabba]

pKVM does not support external trace for protected VMs. Trap
external trace, and add the ExtTrcBuff to make it possible to
check for the feature.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/kvm/hyp/nvhe/pkvm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 9d23a51d7f75..84b5c3f387d8 100644
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -136,6 +136,10 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
 			cptr_set |= CPTR_EL2_TTA;
 	}
 
+	/* Trap External Trace */
+	if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))
+		mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
+
 	vcpu->arch.mdcr_el2 |= mdcr_set;
 	vcpu->arch.mdcr_el2 &= ~mdcr_clear;
 	vcpu->arch.cptr_el2 |= cptr_set;
-- 
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Re: [PATCH v3 01/17] arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 535 bytes --]

On Thu, Dec 14, 2023 at 10:01:41AM +0000, Fuad Tabba wrote:
> Add the Pauth_LR field definitions to ID_AA64ISAR1_EL1, based on
> DDI0601 2023-09.
> 
> These fields aren't used yet. Adding them for completeness and
> consistency (definition already exists for ID_AA64ISAR2_EL1).

This is fine in so far as it goes, though it does make life slightly
easier to do the whole register at once.  There's also a new 0b0010
value in SPECRES here, though not worth making it a blocker:

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v3 02/17] arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 432 bytes --]

On Thu, Dec 14, 2023 at 10:01:42AM +0000, Fuad Tabba wrote:
> Add the ExtTrcBuff field definitions to ID_AA64DFR0_EL1 from
> DDI0601 2023-09.
> 
> This field isn't used yet. Adding it for completeness and because
> it will be used in future patches.

There's also updates for PMSVer, PMUVer and DebugVer, and the addition
of SEBEP and PSSS.  The changes here are fine though

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v3 01/17] arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 366 bytes --]

On Thu, Dec 14, 2023 at 10:42:12AM +0000, Mark Brown wrote:

> This is fine in so far as it goes, though it does make life slightly
> easier to do the whole register at once.  There's also a new 0b0010
> value in SPECRES here, though not worth making it a blocker:

Sorry, was looking at a draft version there - this is fine as per the
current docs (as is patch 2).

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Re: [PATCH v3 03/17] arm64/sysreg: Add missing system register definitions for FGT

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 246 bytes --]

On Thu, Dec 14, 2023 at 10:01:43AM +0000, Fuad Tabba wrote:
> Add the definitions of missing system registers that are
> trappable by fine grain traps. The definitions are based on
> DDI0601 2023-09.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v3 09/17] KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt

[Fuad Tabba]

Hi,

On Thu, Dec 14, 2023 at 10:02 AM Fuad Tabba <tabba@google.com> wrote:
>
> Add the encodings to fine grain trapping fields for HAFGRTR_EL2
> and add the associated handling code in nested virt. Based on
> DDI0601 2023-09. Add the missing field definitions as well,
> both to generate the correct RES0 mask and to be able to toggle
> their FGT bits.

I realized that HAFGRTR_EL2 is present only when both FEAT_AMUv1 and
FEAT_FGT are implemented. Otherwise, direct accesses to it are
UNDEFINED.

I'll fix this when I respin. In the meantime, below is the fix to this
patch. Note that checking for ARM64_HAS_AMU_EXTN is not enough, since,
among other things, it's a weak local cpu feature, i.e., not all cpus
need to have it (and none might).

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h
b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 22f3b916f60c..741d6f0a780a 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -79,6 +79,13 @@ static inline void __activate_traps_fpsimd32(struct
kvm_vcpu *vcpu)
                clr |= ~hfg & __ ## reg ## _nMASK;                      \
        } while(0)

+static inline bool cpu_has_amu(void)
+{
+       u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
+
+       return cpuid_feature_extract_unsigned_field(pfr0,
+               ID_AA64PFR0_EL1_AMU_SHIFT);
+}

 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 {
@@ -157,6 +164,9 @@ static inline void __activate_traps_hfgxtr(struct
kvm_vcpu *vcpu)
        write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
        write_sysreg_s(w_val, SYS_HDFGWTR_EL2);

+       if (!cpu_has_amu())
+               return;
+
        ctxt_sys_reg(hctxt, HAFGRTR_EL2) = read_sysreg_s(SYS_HAFGRTR_EL2);

        r_clr = r_set = 0;
@@ -185,7 +195,9 @@ static inline void
__deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
        write_sysreg_s(ctxt_sys_reg(hctxt, HFGITR_EL2), SYS_HFGITR_EL2);
        write_sysreg_s(ctxt_sys_reg(hctxt, HDFGRTR_EL2), SYS_HDFGRTR_EL2);
        write_sysreg_s(ctxt_sys_reg(hctxt, HDFGWTR_EL2), SYS_HDFGWTR_EL2);
-       write_sysreg_s(ctxt_sys_reg(hctxt, HAFGRTR_EL2), SYS_HAFGRTR_EL2);
+
+       if (cpu_has_amu())
+               write_sysreg_s(ctxt_sys_reg(hctxt, HAFGRTR_EL2),
SYS_HAFGRTR_EL2);
 }

 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)


Cheers,
/fuad





>
> Also add the code for handling FGT trapping, reading of the
> register, to nested virt.
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Fuad Tabba <tabba@google.com>
> ---
>  arch/arm64/include/asm/kvm_host.h       |  1 +
>  arch/arm64/kvm/emulate-nested.c         | 48 +++++++++++++++++++++++++
>  arch/arm64/kvm/hyp/include/hyp/switch.h | 12 +++++++
>  arch/arm64/kvm/sys_regs.c               |  1 +
>  4 files changed, 62 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 824f29f04916..ba14648e2de2 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -443,6 +443,7 @@ enum vcpu_sysreg {
>         HFGITR_EL2,
>         HDFGRTR_EL2,
>         HDFGWTR_EL2,
> +       HAFGRTR_EL2,
>         CNTHP_CTL_EL2,
>         CNTHP_CVAL_EL2,
>         CNTHV_CTL_EL2,
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 89901550db34..431fd429932d 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -1012,6 +1012,7 @@ enum fgt_group_id {
>         HDFGRTR_GROUP,
>         HDFGWTR_GROUP,
>         HFGITR_GROUP,
> +       HAFGRTR_GROUP,
>
>         /* Must be last */
>         __NR_FGT_GROUP_IDS__
> @@ -1689,6 +1690,49 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
>         SR_FGT(SYS_PMCR_EL0,            HDFGWTR, PMCR_EL0, 1),
>         SR_FGT(SYS_PMSWINC_EL0,         HDFGWTR, PMSWINC_EL0, 1),
>         SR_FGT(SYS_OSLAR_EL1,           HDFGWTR, OSLAR_EL1, 1),
> +       /*
> +        * HAFGRTR_EL2
> +        */
> +       SR_FGT(SYS_AMEVTYPER1_EL0(15),  HAFGRTR, AMEVTYPER115_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(14),  HAFGRTR, AMEVTYPER114_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(13),  HAFGRTR, AMEVTYPER113_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(12),  HAFGRTR, AMEVTYPER112_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(11),  HAFGRTR, AMEVTYPER111_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(10),  HAFGRTR, AMEVTYPER110_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(9),   HAFGRTR, AMEVTYPER19_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(8),   HAFGRTR, AMEVTYPER18_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(7),   HAFGRTR, AMEVTYPER17_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(6),   HAFGRTR, AMEVTYPER16_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(5),   HAFGRTR, AMEVTYPER15_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(4),   HAFGRTR, AMEVTYPER14_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(3),   HAFGRTR, AMEVTYPER13_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(2),   HAFGRTR, AMEVTYPER12_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(1),   HAFGRTR, AMEVTYPER11_EL0, 1),
> +       SR_FGT(SYS_AMEVTYPER1_EL0(0),   HAFGRTR, AMEVTYPER10_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(15),   HAFGRTR, AMEVCNTR115_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(14),   HAFGRTR, AMEVCNTR114_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(13),   HAFGRTR, AMEVCNTR113_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(12),   HAFGRTR, AMEVCNTR112_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(11),   HAFGRTR, AMEVCNTR111_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(10),   HAFGRTR, AMEVCNTR110_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(9),    HAFGRTR, AMEVCNTR19_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(8),    HAFGRTR, AMEVCNTR18_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(7),    HAFGRTR, AMEVCNTR17_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(6),    HAFGRTR, AMEVCNTR16_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(5),    HAFGRTR, AMEVCNTR15_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(4),    HAFGRTR, AMEVCNTR14_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(3),    HAFGRTR, AMEVCNTR13_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(2),    HAFGRTR, AMEVCNTR12_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(1),    HAFGRTR, AMEVCNTR11_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR1_EL0(0),    HAFGRTR, AMEVCNTR10_EL0, 1),
> +       SR_FGT(SYS_AMCNTENCLR1_EL0,     HAFGRTR, AMCNTEN1, 1),
> +       SR_FGT(SYS_AMCNTENSET1_EL0,     HAFGRTR, AMCNTEN1, 1),
> +       SR_FGT(SYS_AMCNTENCLR0_EL0,     HAFGRTR, AMCNTEN0, 1),
> +       SR_FGT(SYS_AMCNTENSET0_EL0,     HAFGRTR, AMCNTEN0, 1),
> +       SR_FGT(SYS_AMEVCNTR0_EL0(3),    HAFGRTR, AMEVCNTR03_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR0_EL0(2),    HAFGRTR, AMEVCNTR02_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR0_EL0(1),    HAFGRTR, AMEVCNTR01_EL0, 1),
> +       SR_FGT(SYS_AMEVCNTR0_EL0(0),    HAFGRTR, AMEVCNTR00_EL0, 1),
>  };
>
>  static union trap_config get_trap_config(u32 sysreg)
> @@ -1909,6 +1953,10 @@ bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
>                         val = sanitised_sys_reg(vcpu, HDFGWTR_EL2);
>                 break;
>
> +       case HAFGRTR_GROUP:
> +               val = sanitised_sys_reg(vcpu, HAFGRTR_EL2);
> +               break;
> +
>         case HFGITR_GROUP:
>                 val = sanitised_sys_reg(vcpu, HFGITR_EL2);
>                 switch (tc.fgf) {
> diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
> index 7b4909dfd1f5..22f3b916f60c 100644
> --- a/arch/arm64/kvm/hyp/include/hyp/switch.h
> +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
> @@ -156,6 +156,17 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
>
>         write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
>         write_sysreg_s(w_val, SYS_HDFGWTR_EL2);
> +
> +       ctxt_sys_reg(hctxt, HAFGRTR_EL2) = read_sysreg_s(SYS_HAFGRTR_EL2);
> +
> +       r_clr = r_set = 0;
> +       compute_clr_set(vcpu, HAFGRTR_EL2, r_clr, r_set);
> +
> +       r_val = __HAFGRTR_EL2_nMASK;
> +       r_val |= r_set;
> +       r_val &= ~r_clr;
> +
> +       write_sysreg_s(r_val, SYS_HAFGRTR_EL2);
>  }
>
>  static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
> @@ -174,6 +185,7 @@ static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
>         write_sysreg_s(ctxt_sys_reg(hctxt, HFGITR_EL2), SYS_HFGITR_EL2);
>         write_sysreg_s(ctxt_sys_reg(hctxt, HDFGRTR_EL2), SYS_HDFGRTR_EL2);
>         write_sysreg_s(ctxt_sys_reg(hctxt, HDFGWTR_EL2), SYS_HDFGWTR_EL2);
> +       write_sysreg_s(ctxt_sys_reg(hctxt, HAFGRTR_EL2), SYS_HAFGRTR_EL2);
>  }
>
>  static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 4735e1b37fb3..8bb297a2df38 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -2532,6 +2532,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>         { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
>         EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
>         EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
> +       EL2_REG(HAFGRTR_EL2, access_rw, reset_val, 0),
>         EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
>         EL2_REG(ELR_EL2, access_rw, reset_val, 0),
>         { SYS_DESC(SYS_SP_EL1), access_sp_el1},
> --
> 2.43.0.472.g3155946c3a-goog
>

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Fuad Tabba]

Hi,

On Thu, Dec 14, 2023 at 10:02 AM Fuad Tabba <tabba@google.com> wrote:
>
> There's a lot of boilerplate code for setting and clearing FGT
> bits when activating guest traps. Refactor it into macros. These
> macros will also be used in future patch series.
>
> No functional change intended.
>
> Signed-off-by: Fuad Tabba <tabba@google.com>

And in relation to my email in "PATCH v3 09/17" [*] on HAFGRTR_EL2
being present only when FEAT_AMUv1 is implemented and FEAT_FGT:

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h
b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 58e450180f68..071d6db299f5 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -174,7 +174,9 @@ static inline void __activate_traps_hfgxtr(struct
kvm_vcpu *vcpu)
        update_fgt_traps(HFGITR_EL2);
        update_fgt_traps(HDFGRTR_EL2);
        update_fgt_traps(HDFGWTR_EL2);
-       update_fgt_traps(HAFGRTR_EL2);
+
+       if (cpu_has_amu())
+               update_fgt_traps(HAFGRTR_EL2);
 }

 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)

* https://lore.kernel.org/all/CA+EHjTwrcXjOdo7JG-6fr0YpDq2EtMoTQxngq5H-ELLdjyQG=A@mail.gmail.com/

Cheers,
/fuad





> ---
>  arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++----------------
>  1 file changed, 21 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
> index 17ce40f5b006..e223fc0d5193 100644
> --- a/arch/arm64/kvm/hyp/include/hyp/switch.h
> +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
> @@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
>                 clr |= ~hfg & __ ## reg ## _nMASK;                      \
>         } while(0)
>
> +#define update_fgt_traps_cs(reg, clr, set)                             \
> +       do {                                                            \
> +               struct kvm_cpu_context *hctxt =                         \
> +                       &this_cpu_ptr(&kvm_host_data)->host_ctxt;       \
> +               u64 val, c = 0, s = 0;                                  \
> +                                                                       \
> +               ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);  \
> +               compute_clr_set(vcpu, reg, c, s);                       \
> +               val = __ ## reg ## _nMASK;                              \
> +               val |= (s | set);                                       \
> +               val &= ~(c | clr);                                      \
> +               write_sysreg_s(val, SYS_ ## reg);                       \
> +       } while(0)
> +
> +#define update_fgt_traps(reg)                                          \
> +       update_fgt_traps_cs(reg, 0, 0)
> +
>  /*
>   * Validate the fine grain trap masks.
>   * Check that the masks do not overlap and that all bits are accounted for.
> @@ -146,45 +163,10 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
>         if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
>                 return;
>
> -       ctxt_sys_reg(hctxt, HFGITR_EL2) = read_sysreg_s(SYS_HFGITR_EL2);
> -
> -       r_set = r_clr = 0;
> -       compute_clr_set(vcpu, HFGITR_EL2, r_clr, r_set);
> -       r_val = __HFGITR_EL2_nMASK;
> -       r_val |= r_set;
> -       r_val &= ~r_clr;
> -
> -       write_sysreg_s(r_val, SYS_HFGITR_EL2);
> -
> -       ctxt_sys_reg(hctxt, HDFGRTR_EL2) = read_sysreg_s(SYS_HDFGRTR_EL2);
> -       ctxt_sys_reg(hctxt, HDFGWTR_EL2) = read_sysreg_s(SYS_HDFGWTR_EL2);
> -
> -       r_clr = r_set = w_clr = w_set = 0;
> -
> -       compute_clr_set(vcpu, HDFGRTR_EL2, r_clr, r_set);
> -       compute_clr_set(vcpu, HDFGWTR_EL2, w_clr, w_set);
> -
> -       r_val = __HDFGRTR_EL2_nMASK;
> -       r_val |= r_set;
> -       r_val &= ~r_clr;
> -
> -       w_val = __HDFGWTR_EL2_nMASK;
> -       w_val |= w_set;
> -       w_val &= ~w_clr;
> -
> -       write_sysreg_s(r_val, SYS_HDFGRTR_EL2);
> -       write_sysreg_s(w_val, SYS_HDFGWTR_EL2);
> -
> -       ctxt_sys_reg(hctxt, HAFGRTR_EL2) = read_sysreg_s(SYS_HAFGRTR_EL2);
> -
> -       r_clr = r_set = 0;
> -       compute_clr_set(vcpu, HAFGRTR_EL2, r_clr, r_set);
> -
> -       r_val = __HAFGRTR_EL2_nMASK;
> -       r_val |= r_set;
> -       r_val &= ~r_clr;
> -
> -       write_sysreg_s(r_val, SYS_HAFGRTR_EL2);
> +       update_fgt_traps(HFGITR_EL2);
> +       update_fgt_traps(HDFGRTR_EL2);
> +       update_fgt_traps(HDFGWTR_EL2);
> +       update_fgt_traps(HAFGRTR_EL2);
>  }
>
>  static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
> --
> 2.43.0.472.g3155946c3a-goog
>

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Re: [PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps

[Will Deacon]

On Thu, 14 Dec 2023 10:01:40 +0000, Fuad Tabba wrote:
> Changes from v2:
> - Rebased on arm64/for-next/sysregs, which includes new system
>   register definitions (Mark, Joey)
> - Explicitly trap unsupported HFGxTR_EL2 features rather than
>   relying on its nMASK (Joey)
> - Add new system registers to the auto-generated sysreg rather
>   than hardcoding them (Mark)
> - Drop patch that was meant as RFC
> - Added missing system registers, fields, and  system
>   instructions
> - Split patches that make system register changes
> - Fixes to patches defining allowed features for protected VMs
> - Other minor fixes and tidying up
> 
> [...]

Applied the first four sysreg patches to arm64 (for-next/sysregs), thanks!

[01/17] arm64/sysreg: Add missing Pauth_LR field definitions to ID_AA64ISAR1_EL1
        https://git.kernel.org/arm64/c/3b077ad8cb25
[02/17] arm64/sysreg: Add missing ExtTrcBuff field definition to ID_AA64DFR0_EL1
        https://git.kernel.org/arm64/c/4f101cdcb578
[03/17] arm64/sysreg: Add missing system register definitions for FGT
        https://git.kernel.org/arm64/c/885c6d8e2885
[04/17] arm64/sysreg: Add missing system instruction definitions for FGT
        https://git.kernel.org/arm64/c/4ebee8cebdf6

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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Re: [PATCH v3 13/17] KVM: arm64: Define FGT nMASK bits relative to other fields

[Marc Zyngier]

On Thu, 14 Dec 2023 10:01:53 +0000,
Fuad Tabba <tabba@google.com> wrote:
> 
> Now that RES0 and MASK have full coverage, no speed to manually
> encode nMASK. Calculate it relative to the other fields.

s/speed/need/ ?

	M.

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Re: [PATCH v3 13/17] KVM: arm64: Define FGT nMASK bits relative to other fields

[Fuad Tabba]

On Mon, Dec 18, 2023 at 9:07 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu, 14 Dec 2023 10:01:53 +0000,
> Fuad Tabba <tabba@google.com> wrote:
> >
> > Now that RES0 and MASK have full coverage, no speed to manually
> > encode nMASK. Calculate it relative to the other fields.
>
> s/speed/need/ ?

I might have been in a hurry when I wrote this ;)
/fuad

>         M.
>
> --
> Without deviation from the norm, progress is not possible.

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Marc Zyngier]

On Thu, 14 Dec 2023 10:01:54 +0000,
Fuad Tabba <tabba@google.com> wrote:
> 
> There's a lot of boilerplate code for setting and clearing FGT
> bits when activating guest traps. Refactor it into macros. These
> macros will also be used in future patch series.
> 
> No functional change intended.
> 
> Signed-off-by: Fuad Tabba <tabba@google.com>
> ---
>  arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++----------------
>  1 file changed, 21 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
> index 17ce40f5b006..e223fc0d5193 100644
> --- a/arch/arm64/kvm/hyp/include/hyp/switch.h
> +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
> @@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
>  		clr |= ~hfg & __ ## reg ## _nMASK; 			\
>  	} while(0)
>  
> +#define update_fgt_traps_cs(reg, clr, set)				\
> +	do {								\
> +		struct kvm_cpu_context *hctxt =				\
> +			&this_cpu_ptr(&kvm_host_data)->host_ctxt;	\
> +		u64 val, c = 0, s = 0;					\
> +									\
> +		ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);	\
> +		compute_clr_set(vcpu, reg, c, s);			\

You are referring to a variable name that is in the scope of the macro
user, and not the macro itself. It is so fragile it isn't funny.

Why don't you simply pass the vcpu as a parameter to the function?

Another thing is that this read/write can be expensive. How about not
doing anything when there is no change to the value of the sysreg?

I'll see if I can come up with something.

	M.

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Fuad Tabba]

Hi Marc,

On Mon, Dec 18, 2023 at 9:40 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu, 14 Dec 2023 10:01:54 +0000,
> Fuad Tabba <tabba@google.com> wrote:
> >
> > There's a lot of boilerplate code for setting and clearing FGT
> > bits when activating guest traps. Refactor it into macros. These
> > macros will also be used in future patch series.
> >
> > No functional change intended.
> >
> > Signed-off-by: Fuad Tabba <tabba@google.com>
> > ---
> >  arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++----------------
> >  1 file changed, 21 insertions(+), 39 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
> > index 17ce40f5b006..e223fc0d5193 100644
> > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h
> > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
> > @@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
> >               clr |= ~hfg & __ ## reg ## _nMASK;                      \
> >       } while(0)
> >
> > +#define update_fgt_traps_cs(reg, clr, set)                           \
> > +     do {                                                            \
> > +             struct kvm_cpu_context *hctxt =                         \
> > +                     &this_cpu_ptr(&kvm_host_data)->host_ctxt;       \
> > +             u64 val, c = 0, s = 0;                                  \
> > +                                                                     \
> > +             ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);  \
> > +             compute_clr_set(vcpu, reg, c, s);                       \
>
> You are referring to a variable name that is in the scope of the macro
> user, and not the macro itself. It is so fragile it isn't funny.
>
> Why don't you simply pass the vcpu as a parameter to the function?
>
> Another thing is that this read/write can be expensive. How about not
> doing anything when there is no change to the value of the sysreg?

What do you think of this (spacing will be fixed):

#define update_fgt_traps_cs(vcpu, reg, clr, set)                         \
    do {
                           \
        struct kvm_cpu_context *hctxt =
         \
            &this_cpu_ptr(&kvm_host_data)->host_ctxt;                  \
        u64 val, c = 0, s = 0;
                  \

                             \
        ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);   \
        compute_clr_set(vcpu, reg, c, s);
          \
        val = __ ## reg ## _nMASK;
          \
        val |= (s | set);
                        \
        val &= ~(c | clr);
                       \
        if (ctxt_sys_reg(hctxt, reg) != val)
              \
            write_sysreg_s(val, SYS_ ## reg);
           \
    } while(0)

If it looks good to you, I'll fix it on the respin.

Thanks,
/fuad

>
> I'll see if I can come up with something.
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Marc Zyngier]

On Mon, 18 Dec 2023 09:56:32 +0000,
Fuad Tabba <tabba@google.com> wrote:
> 
> Hi Marc,
> 
> On Mon, Dec 18, 2023 at 9:40 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Thu, 14 Dec 2023 10:01:54 +0000,
> > Fuad Tabba <tabba@google.com> wrote:
> > >
> > > There's a lot of boilerplate code for setting and clearing FGT
> > > bits when activating guest traps. Refactor it into macros. These
> > > macros will also be used in future patch series.
> > >
> > > No functional change intended.
> > >
> > > Signed-off-by: Fuad Tabba <tabba@google.com>
> > > ---
> > >  arch/arm64/kvm/hyp/include/hyp/switch.h | 60 +++++++++----------------
> > >  1 file changed, 21 insertions(+), 39 deletions(-)
> > >
> > > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
> > > index 17ce40f5b006..e223fc0d5193 100644
> > > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h
> > > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
> > > @@ -79,6 +79,23 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
> > >               clr |= ~hfg & __ ## reg ## _nMASK;                      \
> > >       } while(0)
> > >
> > > +#define update_fgt_traps_cs(reg, clr, set)                           \
> > > +     do {                                                            \
> > > +             struct kvm_cpu_context *hctxt =                         \
> > > +                     &this_cpu_ptr(&kvm_host_data)->host_ctxt;       \
> > > +             u64 val, c = 0, s = 0;                                  \
> > > +                                                                     \
> > > +             ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);  \
> > > +             compute_clr_set(vcpu, reg, c, s);                       \
> >
> > You are referring to a variable name that is in the scope of the macro
> > user, and not the macro itself. It is so fragile it isn't funny.
> >
> > Why don't you simply pass the vcpu as a parameter to the function?
> >
> > Another thing is that this read/write can be expensive. How about not
> > doing anything when there is no change to the value of the sysreg?
> 
> What do you think of this (spacing will be fixed):
> 
> #define update_fgt_traps_cs(vcpu, reg, clr, set)                         \
>     do {
>                            \
>         struct kvm_cpu_context *hctxt =
>          \
>             &this_cpu_ptr(&kvm_host_data)->host_ctxt;                  \
>         u64 val, c = 0, s = 0;
>                   \
> 
>                              \
>         ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);   \
>         compute_clr_set(vcpu, reg, c, s);
>           \
>         val = __ ## reg ## _nMASK;
>           \
>         val |= (s | set);
>                         \
>         val &= ~(c | clr);
>                        \
>         if (ctxt_sys_reg(hctxt, reg) != val)
>               \
>             write_sysreg_s(val, SYS_ ## reg);
>            \
>     } while(0)
> 
> If it looks good to you, I'll fix it on the respin.

This is what I have on top at the moment:

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 27077e1f7de2..d56fef44dc31 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -79,22 +79,26 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 		clr |= ~hfg & __ ## reg ## _nMASK; 			\
 	} while(0)
 
-#define update_fgt_traps_cs(reg, clr, set)				\
+#define update_fgt_traps_cs(vcpu, reg, clr, set)			\
 	do {								\
 		struct kvm_cpu_context *hctxt =				\
 			&this_cpu_ptr(&kvm_host_data)->host_ctxt;	\
-		u64 val, c = 0, s = 0;					\
+		u64 c = 0, s = 0;					\
 									\
 		ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg);	\
 		compute_clr_set(vcpu, reg, c, s);			\
-		val = __ ## reg ## _nMASK;				\
-		val |= (s | set);					\
-		val &= ~(c | clr);					\
-		write_sysreg_s(val, SYS_ ## reg);			\
+		s |= set;						\
+		c |= clr;						\
+		if (c || s) {						\
+			u64 val = __ ## reg ## _nMASK;			\
+			val |= s;					\
+			val &= ~c;					\
+			write_sysreg_s(val, SYS_ ## reg);		\
+		}							\
 	} while(0)
 
-#define update_fgt_traps(reg)						\
-	update_fgt_traps_cs(reg, 0, 0)
+#define update_fgt_traps(vcpu, reg)		\
+	update_fgt_traps_cs(vcpu, reg, 0, 0)
 
 /*
  * Validate the fine grain trap masks.
@@ -171,9 +175,9 @@ static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
 	if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
 		return;
 
-	update_fgt_traps(HFGITR_EL2);
-	update_fgt_traps(HDFGRTR_EL2);
-	update_fgt_traps(HDFGWTR_EL2);
+	update_fgt_traps(vcpu, HFGITR_EL2);
+	update_fgt_traps(vcpu, HDFGRTR_EL2);
+	update_fgt_traps(vcpu, HDFGWTR_EL2);
 
 	if (cpu_has_amu())
 		update_fgt_traps(vcpu, HAFGRTR_EL2);

If that seems sensible to you, I'll fold it in, as I'd like to do
without a respin if we can avoid it.

`	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Fuad Tabba]

Hi Marc,

On Mon, Dec 18, 2023 at 11:12 AM Marc Zyngier <maz@kernel.org> wrote:
...
>         if (cpu_has_amu())
>                 update_fgt_traps(vcpu, HAFGRTR_EL2);
>
> If that seems sensible to you, I'll fold it in, as I'd like to do
> without a respin if we can avoid it.

Looks good to me. Thanks Marc!
/fuad

>
> `       M.
>
> --
> Without deviation from the norm, progress is not possible.

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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Marc Zyngier]

On Mon, 18 Dec 2023 11:17:55 +0000,
Fuad Tabba <tabba@google.com> wrote:
> 
> Hi Marc,
> 
> On Mon, Dec 18, 2023 at 11:12 AM Marc Zyngier <maz@kernel.org> wrote:
> ...
> >         if (cpu_has_amu())
> >                 update_fgt_traps(vcpu, HAFGRTR_EL2);
> >
> > If that seems sensible to you, I'll fold it in, as I'd like to do
> > without a respin if we can avoid it.
> 
> Looks good to me. Thanks Marc!

Please have a look at [1] to see what I have done (AMU fixes and my
suggestion for the FGT macros), and let me know if that's OK with you.

I've given it a go on my M2 with NV (only a couple of minor conflicts)
and nothing caught fire.

Thanks,

	M.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=kvm-arm64/fgt-rework

-- 
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Re: [PATCH v3 14/17] KVM: arm64: Macros for setting/clearing FGT bits

[Fuad Tabba]

Hi Marc,

On Mon, Dec 18, 2023 at 12:25 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 18 Dec 2023 11:17:55 +0000,
> Fuad Tabba <tabba@google.com> wrote:
> >
> > Hi Marc,
> >
> > On Mon, Dec 18, 2023 at 11:12 AM Marc Zyngier <maz@kernel.org> wrote:
> > ...
> > >         if (cpu_has_amu())
> > >                 update_fgt_traps(vcpu, HAFGRTR_EL2);
> > >
> > > If that seems sensible to you, I'll fold it in, as I'd like to do
> > > without a respin if we can avoid it.
> >
> > Looks good to me. Thanks Marc!
>
> Please have a look at [1] to see what I have done (AMU fixes and my
> suggestion for the FGT macros), and let me know if that's OK with you.
>
> I've given it a go on my M2 with NV (only a couple of minor conflicts)
> and nothing caught fire.

Both the AMU fixes and the FGT macros look good to me. Thanks for this!

Cheers,
/fuad

>
> Thanks,
>
>         M.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=kvm-arm64/fgt-rework
>
> --
> Without deviation from the norm, progress is not possible.

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Re: (subset) [PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps

[Marc Zyngier]

On Thu, 14 Dec 2023 10:01:40 +0000, Fuad Tabba wrote:
> Changes from v2:
> - Rebased on arm64/for-next/sysregs, which includes new system
>   register definitions (Mark, Joey)
> - Explicitly trap unsupported HFGxTR_EL2 features rather than
>   relying on its nMASK (Joey)
> - Add new system registers to the auto-generated sysreg rather
>   than hardcoding them (Mark)
> - Drop patch that was meant as RFC
> - Added missing system registers, fields, and  system
>   instructions
> - Split patches that make system register changes
> - Fixes to patches defining allowed features for protected VMs
> - Other minor fixes and tidying up
> 
> [...]

Applied to next with the changes agreed on the list.

[05/17] KVM: arm64: Explicitly trap unsupported HFGxTR_EL2 features
        commit: 1565c881c3df053447309ff69ec7fd5dee2085e4
[06/17] KVM: arm64: Add missing HFGxTR_EL2 FGT entries to nested virt
        commit: 9d400eb722bd1be712b007149ff1d8fb2d6470db
[07/17] KVM: arm64: Add missing HFGITR_EL2 FGT entries to nested virt
        commit: 863ac38984a822ff9f4337d70853d771dcf7aae5
[08/17] KVM: arm64: Add bit masks for HAFGRTR_EL2
        commit: f9d6ed0213021ea00af30efbfa33e9a06c0610f2
[09/17] KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt
        commit: 676f482354886caa9b0cfa9236f5d20ac78f8c6a
[10/17] KVM: arm64: Update and fix FGT register masks
        commit: fc04838f9c00fcbc90a8926bbd46928d6fb36477
[11/17] KVM: arm64: Add build validation for FGT trap mask values
        commit: 6c4abbea6d9c09df448b43624074a208c38e68e0
[12/17] KVM: arm64: Use generated FGT RES0 bits instead of specifying them
        commit: 9ff67dd26a9eed9d73dc23aa63e87b16b3382184
[13/17] KVM: arm64: Define FGT nMASK bits relative to other fields
        commit: 5f6bd3f3daaaab8559ad7d2266ba38345231b7ae
[14/17] KVM: arm64: Macros for setting/clearing FGT bits
        commit: 0ccd901da1886cf9dc53ab36ad8f1160b65e41f1
[15/17] KVM: arm64: Fix which features are marked as allowed for protected VMs
        commit: 73e3ce3f4a0e561e24ca71b20de00f03b427981e
[16/17] KVM: arm64: Mark PAuth as a restricted feature for protected VMs
        commit: 21de26dbc5170dde8e4dfbfa1ecb77804ed6a377
[17/17] KVM: arm64: Trap external trace for protected VMs
        commit: 9d52612690985fc0ee1ae1fbad61530a4f6bbb53

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.



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Re: (subset) [PATCH v3 00/17] KVM: arm64: Fixes to fine grain traps and pKVM traps

[Fuad Tabba]

On Mon, Dec 18, 2023 at 5:11 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu, 14 Dec 2023 10:01:40 +0000, Fuad Tabba wrote:
> > Changes from v2:
> > - Rebased on arm64/for-next/sysregs, which includes new system
> >   register definitions (Mark, Joey)
> > - Explicitly trap unsupported HFGxTR_EL2 features rather than
> >   relying on its nMASK (Joey)
> > - Add new system registers to the auto-generated sysreg rather
> >   than hardcoding them (Mark)
> > - Drop patch that was meant as RFC
> > - Added missing system registers, fields, and  system
> >   instructions
> > - Split patches that make system register changes
> > - Fixes to patches defining allowed features for protected VMs
> > - Other minor fixes and tidying up
> >
> > [...]
>
> Applied to next with the changes agreed on the list.

Thank you!
/fuad

>
> [05/17] KVM: arm64: Explicitly trap unsupported HFGxTR_EL2 features
>         commit: 1565c881c3df053447309ff69ec7fd5dee2085e4
> [06/17] KVM: arm64: Add missing HFGxTR_EL2 FGT entries to nested virt
>         commit: 9d400eb722bd1be712b007149ff1d8fb2d6470db
> [07/17] KVM: arm64: Add missing HFGITR_EL2 FGT entries to nested virt
>         commit: 863ac38984a822ff9f4337d70853d771dcf7aae5
> [08/17] KVM: arm64: Add bit masks for HAFGRTR_EL2
>         commit: f9d6ed0213021ea00af30efbfa33e9a06c0610f2
> [09/17] KVM: arm64: Handle HAFGRTR_EL2 trapping in nested virt
>         commit: 676f482354886caa9b0cfa9236f5d20ac78f8c6a
> [10/17] KVM: arm64: Update and fix FGT register masks
>         commit: fc04838f9c00fcbc90a8926bbd46928d6fb36477
> [11/17] KVM: arm64: Add build validation for FGT trap mask values
>         commit: 6c4abbea6d9c09df448b43624074a208c38e68e0
> [12/17] KVM: arm64: Use generated FGT RES0 bits instead of specifying them
>         commit: 9ff67dd26a9eed9d73dc23aa63e87b16b3382184
> [13/17] KVM: arm64: Define FGT nMASK bits relative to other fields
>         commit: 5f6bd3f3daaaab8559ad7d2266ba38345231b7ae
> [14/17] KVM: arm64: Macros for setting/clearing FGT bits
>         commit: 0ccd901da1886cf9dc53ab36ad8f1160b65e41f1
> [15/17] KVM: arm64: Fix which features are marked as allowed for protected VMs
>         commit: 73e3ce3f4a0e561e24ca71b20de00f03b427981e
> [16/17] KVM: arm64: Mark PAuth as a restricted feature for protected VMs
>         commit: 21de26dbc5170dde8e4dfbfa1ecb77804ed6a377
> [17/17] KVM: arm64: Trap external trace for protected VMs
>         commit: 9d52612690985fc0ee1ae1fbad61530a4f6bbb53
>
> Cheers,
>
>         M.
> --
> Without deviation from the norm, progress is not possible.
>
>

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