From: Marc Zyngier <marc.zyngier@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: leif.lindholm@linaro.org, linux-efi@vger.kernel.org,
steve.mcintyre@linaro.org, linux@armlinux.org.uk,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] efi/arm: enable CP15 DMB instructions before cleaning the cache
Date: Sat, 30 Mar 2019 09:50:32 +0000 [thread overview]
Message-ID: <86y34w668n.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20190329182418.29592-1-ard.biesheuvel@linaro.org>
Hi Ard,
On Fri, 29 Mar 2019 18:24:18 +0000,
Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>
> The EFI stub is entered with the caches and MMU enabled by the
> firmware, and once the stub is ready to hand over to the decompressor,
> we clean and disable the caches.
>
> The cache clean routines use CP15 barrier instructions, which can be
> disabled via SCTLR. Normally, when using the provided cache handling
> routines to enable the caches and MMU, this bit is enabled as well.
> However, but since we entered the stub with the caches already enabled,
> this routine is not executed before we call the cache clean routines,
> resulting in undefined instruction exceptions if the firmware never
> enabled this bit.
>
> So set the bit explicitly in the EFI entry code.
>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> arch/arm/boot/compressed/head.S | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 6c7ccb428c07..62a49356fca3 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -1438,6 +1438,16 @@ ENTRY(efi_stub_entry)
>
> @ Preserve return value of efi_entry() in r4
> mov r4, r0
> +
> + @ our cache maintenance code relies on CP15 barrier instructions
> + @ but since we arrived here with the MMU and caches configured
> + @ by UEFI, we must ensure that the use of those instructions is
> + @ enabled in the SCTLR register, since we never executed our own
> + @ cache enable routine, which is normally in charge of this.
> + mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
> + orr r1, r1, #(1 << 5) @ CP15 barrier instructions
> + mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
> +
To be on the safe side, you could add an isb here. I'm pretty sure it
is immaterial on any ARMv7 core, but hey, I'm paranoid.
With that:
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks,
M.
--
Jazz is not dead, it just smell funny.
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next prev parent reply other threads:[~2019-03-30 9:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-29 18:24 [PATCH] efi/arm: enable CP15 DMB instructions before cleaning the cache Ard Biesheuvel
2019-03-30 9:50 ` Marc Zyngier [this message]
2019-03-30 13:10 ` Ard Biesheuvel
2019-03-31 8:47 ` Marc Zyngier
2019-04-07 18:19 ` Ard Biesheuvel
2019-04-08 9:11 ` Marc Zyngier
2019-04-08 9:20 ` Vladimir Murzin
2019-04-08 21:38 ` Ard Biesheuvel
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