From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB17DC44501 for ; Tue, 14 Jul 2026 07:23:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DHMaA5fIY9CPD3euCNH1DVbe8+u3GtJConS0mtyirDE=; b=FN66q1VfcaOfXEwOeP0UXKRDxk yH0x91aI6uA7Ct3Pvj6Ox6wubHligTYaxJ+BEYGrA2F94BD9SSZNkAR/QjS9U155jy6FAK9P8V2CI 1fRsJCrKrA6q62Il3ahEtozuuNvp4LqGOn56iIz/gda0hben5GTHzvd2yPy0w/dtHmoFDZ6Ev+qM0 oTSqjvfyS3axs08HdOP8UVl89psJEzUss7PkIqS+FU97td1x6r1+eeFhxGs0wdgGWrqfyZtlWHEfM 6FALobarPXaCt988cmeYy0LZXZXvtdFjVMDizApp9Y0GxeiRpLpuua2R44mv4I0vYcUmVL/kjXI/j XhitXCcw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjXUK-0000000B9L9-2spR; Tue, 14 Jul 2026 07:23:32 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjXUI-0000000B9Kx-3PEl for linux-arm-kernel@lists.infradead.org; Tue, 14 Jul 2026 07:23:30 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id BBAF460120; Tue, 14 Jul 2026 07:23:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7072E1F000E9; Tue, 14 Jul 2026 07:23:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784013809; bh=DHMaA5fIY9CPD3euCNH1DVbe8+u3GtJConS0mtyirDE=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=KrUD7qAix+O1nnUiz5T1cKwig3QocEVMPuz5nExlA3jgejsewFnr7YeJIl+YwkOnW 3zRSqHH951TNy2SeJoRkPNJlTMXEjh0l8iNsfYNuW147Y2Z8oRgXlojOjRRgpotg2v pvLMXuIffPDlcIevubp4kZtquq8gJs/mYfPELF51xibv7+HgIUkG+HPubq9BeSXr1V jsj3DbUuf8Kxwjty1gcma0qoXZzzRJn9tzOFYoZZpt1Wx1YRj+ulbLzz8e1IfMdKeu ZABBwL62TMSFY+/LOV6P5Y02pEIYzHG++zSIPwJmz/paAtnRwkDQxo2+PRQWvjl3LY QF9W3WrBZiu6Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wjXUF-00000004lba-0qk6; Tue, 14 Jul 2026 07:23:27 +0000 Date: Tue, 14 Jul 2026 08:23:26 +0100 Message-ID: <86zezunifl.wl-maz@kernel.org> From: Marc Zyngier To: Tian Zheng Cc: Leonardo Bras , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 3/6] KVM: arm64: Add auto DBM support for hardware dirty tracking In-Reply-To: <8f949334-3ce7-44f4-b6da-f08a4126affd@huawei.com> References: <20260709104026.2612599-1-zhengtian10@huawei.com> <20260709104026.2612599-4-zhengtian10@huawei.com> <8f949334-3ce7-44f4-b6da-f08a4126affd@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhengtian10@huawei.com, leo.bras@arm.com, oupton@kernel.org, catalin.marinas@arm.com, will@kernel.org, yuzenghui@huawei.com, wangzhou1@hisilicon.com, yangjinqian1@huawei.com, caijian11@h-partners.com, liuyonglong@huawei.com, yezhenyu2@huawei.com, yubihong@huawei.com, linuxarm@huawei.com, joey.gouly@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, seiden@linux.ibm.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 14 Jul 2026 02:14:45 +0100, Tian Zheng wrote: > > > On 7/13/2026 7:17 PM, Leonardo Bras wrote: > > On Thu, Jul 09, 2026 at 06:40:23PM +0800, Tian Zheng wrote: > >> The DBM (Dirty Bit Modifier) attribute, introduced in ARMv8.1, enables > >> hardware to automatically promote write-clean pages to write-dirty. This > >> prevents the guest from being trapped in EL2 due to missing write > >> permissions. > >> > >> In this design, DBM is controlled by the page-table level flag > >> KVM_PGTABLE_S2_DBM rather than per-PTE software flags. DBM is > >> automatically set for writable non-device pages when the page-table has > >> KVM_PGTABLE_S2_DBM flag, which is determined at MMU init time based on > >> hardware capability. > >> > >> The DBM bit is set in stage2_set_prot_attr() for initial mappings and > >> hugepage splitting, and directly manipulated in > >> kvm_pgtable_stage2_relax_perms() when removing write-protection. On > >> W->RO downgrade, DBM is cleared to prevent hardware from silently > >> upgrading RO+DBM back to W+dirty, which would bypass KVM's write > >> tracking. > >> > >> kvm_pgtable_stage2_pte_prot() does not extract the DBM bit back into > >> enum kvm_pgtable_prot because DBM is a page-table policy determined by > >> pgt->flags, not a per-PTE property. Callers should check > >> pgt->flags & KVM_PGTABLE_S2_DBM instead. > >> > >> This ensures DBM is consistently applied across all PTEs, including > >> during hugepage splitting where child PTEs inherit DBM from the parent > >> block entry via the pgt->flags mechanism. > >> > >> Safety: DBM bit is only interpreted by hardware when VTCR_EL2.HD=1. > >> When HDBSS is not enabled (HD=0), ARM architecture guarantees hardware > >> completely ignores DBM bit in PTEs. > >> > >> Co-developed-by: Eillon > >> Signed-off-by: Eillon > >> Co-developed-by: Leonardo Bras > >> Signed-off-by: Leonardo Bras > > Hello Tian, > > > > Have you added the above tags due to this patch being based on the below? > > https://lore.kernel.org/all/20260629111820.1873540-2-leo.bras@arm.com/ > > > > Thanks! > > Leo > > Hi Leo, > > > Yes, I added your Signed-off-by because the DBM-related code in this patch You really can't do that. Only Leo can give his SoB, you can't forge it yourself. > > is based on your implementation in: > > https://lore.kernel.org/all/20260629111820.1873540-2-leo.bras@arm.com/ Then take the patch as is, and add to it as a separate patch. Or work out in private with Leo whether he's happy with a Co-dev. But never do that unilaterally. Thanks, M. -- Without deviation from the norm, progress is not possible.