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Mon, 23 Mar 2026 13:37:46 +0000 Date: Mon, 23 Mar 2026 13:37:46 +0000 Message-ID: <86zf3y4qfp.wl-maz@kernel.org> From: Marc Zyngier To: Javier Achirica Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@kernel.org Subject: Re: [PATCH v1] irqchip: fix mask alignment in gic-v2m In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jachirica@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260323_063750_115442_2D557926 X-CRM114-Status: GOOD ( 21.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 21 Mar 2026 14:12:16 +0000, Javier Achirica wrote: > > commit 2ef3886ce626dcdab0cbc452dbbebc19f57133d8 ("irqchip/gic-v2m: Handle > Multiple MSI base IRQ Alignment") introduced a regression in kernel 6.12.58 > affecting PCIe devices using GICv2m MSI on a Qualcomm (arm64) platform. > > It uses nr_irqs parameter to generate a mask to align the MSI base address, > but this mask isn't properly generated when nr_irqs isn't a power of two. > This bug was found while adding support for the TCL HH500V router in OpenWrt. > > This patch fixes the issue, can be cleanly applied to the 6.12.x tree and, > with a small fuzz, to 7.0.x. > > Signed-off-by: Javier Achirica > Cc: stable@vger.kernel.org > --- > --- a/drivers/irqchip/irq-gic-v2m.c 2026-03-20 09:45:22.170192561 +0100 > +++ b/drivers/irqchip/irq-gic-v2m.c 2026-03-20 09:45:26.284210783 +0100 > @@ -158,7 +158,7 @@ > struct v2m_data *v2m = NULL, *tmp; > int hwirq, i, err = 0; > unsigned long offset; > - unsigned long align_mask = nr_irqs - 1; > + unsigned long align_mask = roundup_pow_of_two(nr_irqs) - 1; > > spin_lock(&v2m_lock); > list_for_each_entry(tmp, &v2m_nodes, entry) { > This looks wrong for a bunch of reasons: - you're hacking the allocation path, but not the free path -- what could possibly go wrong? - nr_irqs not being a power of two to start with is more indicative of a bug somewhere else in the system. The only case where we allocate more than a single IRQ at a time is for Multi-MSI, and that is definitely a power-of-two construct. I have seen other reports, all concerning QC based HW allocating silly (aka non Po2) numbers of interrupts for Nulti-MSI devices, and I think we should instead address the root cause, most likely in the PCI code. Thanks, M. -- Without deviation from the norm, progress is not possible.