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Fri, 30 Jan 2026 17:26:39 +0000 Date: Fri, 30 Jan 2026 17:26:39 +0000 Message-ID: <86zf5v9flc.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "yuzenghui@huawei.com" , Timothy Hayes , Suzuki Poulose , nd , "peter.maydell@linaro.org" , "kvmarm@lists.linux.dev" , "jonathan.cameron@huawei.com" , "linux-arm-kernel@lists.infradead.org" , "kvm@vger.kernel.org" , Joey Gouly , "lpieralisi@kernel.org" , "oliver.upton@linux.dev" Subject: Re: [PATCH v4 11/36] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE In-Reply-To: <6a45dd02fdd2e70e0722dc5b3087ecfb18f01e98.camel@arm.com> References: <20260128175919.3828384-1-sascha.bischoff@arm.com> <20260128175919.3828384-12-sascha.bischoff@arm.com> <861pj7baav.wl-maz@kernel.org> <6a45dd02fdd2e70e0722dc5b3087ecfb18f01e98.camel@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, yuzenghui@huawei.com, Timothy.Hayes@arm.com, Suzuki.Poulose@arm.com, nd@arm.com, peter.maydell@linaro.org, kvmarm@lists.linux.dev, jonathan.cameron@huawei.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey.Gouly@arm.com, lpieralisi@kernel.org, oliver.upton@linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 30 Jan 2026 17:13:18 +0000, Sascha Bischoff wrote: >=20 > On Fri, 2026-01-30 at 11:38 +0000, Marc Zyngier wrote: > > On Wed, 28 Jan 2026 18:02:09 +0000, > > Sascha Bischoff wrote: > > >=20 > > > Set the guest's view of the GCIE field to IMP when running a GICv5 > > > VM, > > > NI otherwise. Reject any writes to the register that try to do > > > anything but set GCIE to IMP when running a GICv5 VM. > > >=20 > > > As part of this change, we're also required to extend > > > vgic_is_v3_compat() to check for the actual vgic_model. This has > > > one > > > potential issue - if any of the vgic_is_v*() checks are used prior > > > to > > > setting the vgic_model (that is, before kvm_vgic_create) then > > > vgic_model will be set to 0, which can result in a false-positive. > > >=20 > > > Co-authored-by: Timothy Hayes > > > Signed-off-by: Timothy Hayes > > > Signed-off-by: Sascha Bischoff > > > Reviewed-by: Jonathan Cameron > > > --- > > > =C2=A0arch/arm64/kvm/sys_regs.c=C2=A0 | 42 ++++++++++++++++++++++++++= ++++---- > > > ---- > > > =C2=A0arch/arm64/kvm/vgic/vgic.h | 10 ++++++++- > > > =C2=A02 files changed, 43 insertions(+), 9 deletions(-) > > >=20 > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > > index 88a57ca36d96..73dd2bd85c4f 100644 > > > --- a/arch/arm64/kvm/sys_regs.c > > > +++ b/arch/arm64/kvm/sys_regs.c > > > @@ -1758,6 +1758,7 @@ static u8 pmuver_to_perfmon(u8 pmuver) > > > =C2=A0 > > > =C2=A0static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, > > > u64 val); > > > =C2=A0static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, > > > u64 val); > > > +static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, > > > u64 val); > > > =C2=A0static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, > > > u64 val); > > > =C2=A0 > > > =C2=A0/* Read a sanitised cpufeature ID register by sys_reg_desc */ > > > @@ -1783,10 +1784,7 @@ static u64 __kvm_read_sanitised_id_reg(const > > > struct kvm_vcpu *vcpu, > > > =C2=A0 val =3D sanitise_id_aa64pfr1_el1(vcpu, val); > > > =C2=A0 break; > > > =C2=A0 case SYS_ID_AA64PFR2_EL1: > > > - val &=3D ID_AA64PFR2_EL1_FPMR | > > > - (kvm_has_mte(vcpu->kvm) ? > > > - ID_AA64PFR2_EL1_MTEFAR | > > > ID_AA64PFR2_EL1_MTESTOREONLY : > > > - 0); > > > + val =3D sanitise_id_aa64pfr2_el1(vcpu, val); > > > =C2=A0 break; > > > =C2=A0 case SYS_ID_AA64ISAR1_EL1: > > > =C2=A0 if (!vcpu_has_ptrauth(vcpu)) > > > @@ -2024,6 +2022,23 @@ static u64 sanitise_id_aa64pfr1_el1(const > > > struct kvm_vcpu *vcpu, u64 val) > > > =C2=A0 return val; > > > =C2=A0} > > > =C2=A0 > > > +static u64 sanitise_id_aa64pfr2_el1(const struct kvm_vcpu *vcpu, > > > u64 val) > > > +{ > > > + val &=3D ID_AA64PFR2_EL1_FPMR | > > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ID_AA64PFR2_EL1_MTEFAR | > > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ID_AA64PFR2_EL1_MTESTOREONLY; > > > + > > > + if (!kvm_has_mte(vcpu->kvm)) { > > > + val &=3D ~ID_AA64PFR2_EL1_MTEFAR; > > > + val &=3D ~ID_AA64PFR2_EL1_MTESTOREONLY; > > > + } > > > + > > > + if (vgic_is_v5(vcpu->kvm)) > > > + val |=3D SYS_FIELD_PREP_ENUM(ID_AA64PFR2_EL1, GCIE, > > > IMP); > >=20 > > You probably want to clear the field before or'ing something in, or > > you may be promising more than we'd expect. >=20 > The GCIE field should already be zeroed at this point as it is filtered > out to begin with. If we have GICv5 (so FEAT_GCIE) we're explicitly > setting this field to IMP, else NI. As you can tell by now, I can't read. Apologies for the noise. Thanks, M. --=20 Without deviation from the norm, progress is not possible.