From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB3E1C44501 for ; Wed, 21 Jan 2026 10:50:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=22kDOirRPzGW5TAXpkreNZN/j+FFDXEo824mnYGHqXM=; b=b/oqfrc/zKKdYpQJVfC3qHwAJu Z4zXCKeRI0HD18UvlWQiKwthyCY6Z4vaaHsJfndqJ1xTmw5nyl9bUuSAdPhlUYQFF6MqZbZ8WK7DL GQhp+mNefsAl97nZEcTiN6tOl8B4chllQ3uZ6vxJ506Xi/gXFkj7X3Tm0z1TNmXeS9tgnJD0KfZoQ vSGTivcWUCEi09rhkw71FwVpDCOY3crmU4R9ASPzujdK/nWBwGGafo1haRSYe6Y/X4DQMzfXhlKtL 1T+hTeIZjMCF1dZulqUKOi29T0DInKYeeatbbd/HUhOVHSooZcG7oMFgsJKIgSiobJrP6zIxCyUHV gVxrprVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1viVnY-00000005IpS-0NiX; Wed, 21 Jan 2026 10:50:52 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1viVnU-00000005Ip2-2eeZ for linux-arm-kernel@lists.infradead.org; Wed, 21 Jan 2026 10:50:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 00ACA429CA; Wed, 21 Jan 2026 10:50:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC326C116D0; Wed, 21 Jan 2026 10:50:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768992647; bh=CfWWd4eTZ7SIvAFdgkWvswQfPdfwTP4jeQ6wPYFjh1o=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=laLO8FnWyyK8MtpwGzmwWyciuntO3Rup/T85ja0myQmL46b8N413Bbvq6LyRXfwHp nVOca27zcoxzQAA4eLhyaPdrQoQaa9PulWCGI3/ZouvXpI2AAcHynevgy151ZLE9eu INhmN9DQUJhIaffOlnhBg6JhhPTqRkiBgNPSeGDyqFe06PHmQuSabsK1tNhnnhnaf9 lPcunAeH/9XixAVOXdaTA1TK7DrbhlX/IpeZokjzWof3T+4u6t7xKos+lrzg1aStSz 04GLDK0nlwoVRxFgLYGvS+77+10oXNG4D1AchkGl1HbZgDvrx1z+f7oWKir5z+gyXp sVSSKSRmkl8iA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1viVnR-00000004HPP-2D8L; Wed, 21 Jan 2026 10:50:45 +0000 Date: Wed, 21 Jan 2026 10:50:45 +0000 Message-ID: <86zf67b5oa.wl-maz@kernel.org> From: Marc Zyngier To: Nathan Chancellor Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Alexandru Elisei , Sascha Bischoff , Quentin Perret , Fuad Tabba , Sebastian Ene Subject: Re: [PATCH v2 4/6] KVM: arm64: Account for RES1 bits in DECLARE_FEAT_MAP() and co In-Reply-To: <20260120211558.GA834868@ax162> References: <20251210173024.561160-1-maz@kernel.org> <20251210173024.561160-5-maz@kernel.org> <20260120211558.GA834868@ax162> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: nathan@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, Sascha.Bischoff@arm.com, qperret@google.com, tabba@google.com, sebastianene@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260121_025048_716719_FAC56B4A X-CRM114-Status: GOOD ( 30.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Nathan, Thanks for reporting this. On Tue, 20 Jan 2026 21:15:58 +0000, Nathan Chancellor wrote: > > Hi Marc, > > On Wed, Dec 10, 2025 at 05:30:22PM +0000, Marc Zyngier wrote: > > None of the registers we manage in the feature dependency infrastructure > > so far has any RES1 bit. This is about to change, as VTCR_EL2 has > > its bit 31 being RES1. > > > > In order to not fail the consistency checks by not describing a bit, > > add RES1 bits to the set of immutable bits. This requires some extra > > surgery for the FGT handling, as we now need to track RES1 bits there > > as well. > > > > There are no RES1 FGT bits *yet*. Watch this space. > > > > Signed-off-by: Marc Zyngier > > After this change in -next as commit c259d763e6b0 ("KVM: arm64: Account > for RES1 bits in DECLARE_FEAT_MAP() and co"), I am seeing several > "undefined behavior" errors on my two arm64 boxes. > > $ journalctl -k -g '(Linux version|kvm)' --no-hostname -o cat > Linux version 6.19.0-rc4-00014-gc259d763e6b0 (nathan@framework-amd-ryzen-maxplus-395) (aarch64-linux-gcc (GCC) 15.2.0, GNU ld (GNU Binutils) 2.45) #1 SMP PREEMPT_DYNAMIC Tue Jan 20 13:59:52 MST 2026 > kvm [1]: nv: 568 coarse grained trap handlers > kvm [1]: Undefined hfgrtr_masks behaviour, bits fff7ffffffffffff > kvm [1]: Undefined hfgwtr_masks behaviour, bits fff7baffe9db39fb > kvm [1]: Undefined hfgitr_masks behaviour, bits dfffffffffffffff > kvm [1]: Undefined hdfgrtr_masks behaviour, bits fffdfb3fffcffeff > kvm [1]: Undefined hdfgwtr_masks behaviour, bits 73f7763bbfbffdbf > kvm [1]: Undefined hafgrtr_masks behaviour, bits 0003fffffffe001f > kvm [1]: Undefined hfgrtr2_masks behaviour, bits 0000000000007fff > kvm [1]: Undefined hfgwtr2_masks behaviour, bits 0000000000007ffd > kvm [1]: Undefined hfgitr2_masks behaviour, bits 0000000000000003 > kvm [1]: Undefined hdfgrtr2_masks behaviour, bits 0000000001dfffff > kvm [1]: Undefined hdfgwtr2_masks behaviour, bits 0000000001f9ffbf > kvm [1]: IPA Size Limit: 44 bits > kvm [1]: vgic-v2@c0e0000 > kvm [1]: GICv3 sysreg trapping enabled ([C], reduced performance) > kvm [1]: GIC system register CPU interface enabled > kvm [1]: vgic interrupt IRQ9 > kvm [1]: Hyp nVHE mode initialized successfully Let me guess: Cortex-A72 or similarly ancient ARM-designed CPUs, as hinted by the lack of GICv3 TDIR control? Then these do not have FEAT_FGT. The issue stems from the fact that as an optimisation, we skip the parsing of the FGT trap table on such hardware, which also results in the FGT masks of known bits not being updated. We then compute the effective feature map, and discover that the two don't match. It was harmless so far, as we were only dealing with RES0 bits, and assuming that anything that wasn't a RES0 bit was a stateful bit. With the introduction of RES1 handling, we've run out of luck. To be clear, that's just a warning, not a functional issue. At this point, I don't think the above "optimisation" is worth having. This is only done *once*, at boot time, so the gain is extremely small. I'd like the checks to be effective irrespective of the HW the kernel runs on, which is consistent with what we do for other tables describing the architectural state. Anyway, I came up with the following hack, which performs the checks, but avoid inserting the FGT information in the sysreg xarray if the HW doesn't support it, as a memory saving measure. Please let me know if that helps (it does on my old boxes). Thanks, M. diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index 88336336efc9f..fa8fa09de67dc 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2284,9 +2284,6 @@ int __init populate_nv_trap_config(void) kvm_info("nv: %ld coarse grained trap handlers\n", ARRAY_SIZE(encoding_to_cgt)); - if (!cpus_have_final_cap(ARM64_HAS_FGT)) - goto check_mcb; - for (int i = 0; i < ARRAY_SIZE(encoding_to_fgt); i++) { const struct encoding_to_trap_config *fgt = &encoding_to_fgt[i]; union trap_config tc; @@ -2306,6 +2303,15 @@ int __init populate_nv_trap_config(void) } tc.val |= fgt->tc.val; + + if (!aggregate_fgt(tc)) { + ret = -EINVAL; + print_nv_trap_error(fgt, "FGT bit is reserved", ret); + } + + if (!cpus_have_final_cap(ARM64_HAS_FGT)) + continue; + prev = xa_store(&sr_forward_xa, enc, xa_mk_value(tc.val), GFP_KERNEL); @@ -2313,11 +2319,6 @@ int __init populate_nv_trap_config(void) ret = xa_err(prev); print_nv_trap_error(fgt, "Failed FGT insertion", ret); } - - if (!aggregate_fgt(tc)) { - ret = -EINVAL; - print_nv_trap_error(fgt, "FGT bit is reserved", ret); - } } } @@ -2333,7 +2334,6 @@ int __init populate_nv_trap_config(void) kvm_info("nv: %ld fine grained trap handlers\n", ARRAY_SIZE(encoding_to_fgt)); -check_mcb: for (int id = __MULTIPLE_CONTROL_BITS__; id < __COMPLEX_CONDITIONS__; id++) { const enum cgt_group_id *cgids; -- Without deviation from the norm, progress is not possible.