From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6C45CCD183 for ; Thu, 16 Oct 2025 09:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0c/0XiR3fhd4346LXVwjglnOtg2fMdYnOjWWYgJ7Vyo=; b=bAKqFAe0svTCNyQsqGlhNx6JTc T4aIpX0qxw310yxidv1AmYkue+Fsn9aCMjzkgkNqgi9GHoGMrtQ3+6ohDSBc8YGTHE8rECIidgfXS olNGxc6qAcnZj49hltj5vt/7ICFte85xZL+MoOZm5ieoPauJhfhhBnoNVMxde+YKotjzMG+U0Xwjv IEfKd1QfcvjPcps/vBTVCqgF/uswMRhzJsMVhHEiSIwH3NwkplLQM67dYeDHcJpHBqt7J3dF/sAWY iJbwUqIlgBZVi2AlsDb7eaTr0qa+dRErC7yRNuatRxbqvlxZDT4aM3AS5lsEye3gDiVUEu8IINrHM tvAfe55g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v9KQj-00000004EgA-3Mlp; Thu, 16 Oct 2025 09:37:53 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v9KQh-00000004Efn-2cRE for linux-arm-kernel@lists.infradead.org; Thu, 16 Oct 2025 09:37:51 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 11A46603CE; Thu, 16 Oct 2025 09:37:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B424CC4CEF1; Thu, 16 Oct 2025 09:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760607470; bh=XPlGlxBWqfjNhhG6D89xRLITvczn/ASxGgB6gYdc+c0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=L0vriKYf3WosUY2Ziw0RN3Oxu1DQ6a0T2Y1wVpytBKbRw7NvZFFhwWCK92oKUluH7 I+jdo/GGHIW4V6GLb2VZHs1MUU0X1QTMIZROV2XRq5AxESbUb+DU5/2Fy9YKuH90Cm +q7txJQEuNkSGwWVfDIjixh/f/4wtOViuMq6u0ppV10nkCALuaPtSH2/oVWnXg86TN uxU5SjLJYs4WOgpDGYoZKVyC7pnPTSn6nbbh82DmpKSFfaOiDvNkKQdqjTvhLo12Fu R41slXUDYkqQoISUAjz20gc3as/lrsq1YbsXpGfnqQ1DIJVhFUk3zu9J4ylVg1vcEw ulN5X1P12a7ZQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v9KQe-0000000ESbz-1Tzt; Thu, 16 Oct 2025 09:37:48 +0000 Date: Thu, 16 Oct 2025 10:37:47 +0100 Message-ID: <86zf9rw5jo.wl-maz@kernel.org> From: Marc Zyngier To: Yifan Wu Cc: , , , , , , , , , , , , Subject: Re: [PATCH] gic: increase the arch_timer priority to avoid hardlockup In-Reply-To: <861pn3xqug.wl-maz@kernel.org> References: <20251016034733.3092375-1-wuyifan50@huawei.com> <861pn3xqug.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: wuyifan50@huawei.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com, xiaqinxin@huawei.com, yangyicong@huawei.com, wangyushan12@huawei.com, wangzhou1@hisilicon.com, prime.zeng@hisilicon.com, xuwei5@huawei.com, fanghao11@huawei.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 16 Oct 2025 08:12:23 +0100, Marc Zyngier wrote: > > On Thu, 16 Oct 2025 04:47:33 +0100, > Yifan Wu wrote: > > > > From: Qinxin Xia > > > > ---------------------------------------------------------------------- > > > > On HIP12, when GIC receives multiple interrupts of the same priority and > > different types, the interrupts are selected in the following sequence: > > SPI > LPI > SGI > PPI. This scheduling rule may cause PPI starvation. > > To prevent starvation from triggering system watchdog hardlockup, the > > interrupt priority is explicitly increased in the arch_timer driver. > > No. This breaks pseudo NMIs, and is way too invasive. Also, how about > the other PPIs? Frankly, if your GIC is not able to do some form of > fair delivery, then it probably isn't fit for purpose. Thinking about this some more, this is even worse than it looks. Your GIC is, one way or another, implementing the interrupt classes as a form of extra (sub-)priority bits, which breaks everything. How do you want to solve this? By adding some other hardcoded priority scheme. That's just as bad as the situation you have now. What happens if, for example, your have a CPU with a screaming timer interrupt and that another CPU tries to IPI it? Same problem, just pushed one level further. You cannot solve this by just moving from one bad priority scheme to another. There is simply no priority scheme that can solve this, because priorities are the exact opposite of fairness, and fairness is the property we are relying on. Thanks, M. -- Without deviation from the norm, progress is not possible.