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From: Marc Zyngier <maz@kernel.org>
To: Sergey Shtylyov <s.shtylyov@omp.ru>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] irqchip/gic: prevent buffer overflow in gic_ipi_send_mask()
Date: Tue, 10 Sep 2024 08:38:12 +0100	[thread overview]
Message-ID: <86zfog6jrv.wl-maz@kernel.org> (raw)
In-Reply-To: <052d20d5-e8e4-3133-4fa0-1c026ffb4209@omp.ru>

On Mon, 09 Sep 2024 20:48:24 +0100,
Sergey Shtylyov <s.shtylyov@omp.ru> wrote:
> 
>    GICv2 spec does talk about 1-N and N-N interrupt handling modes;
> at the same time, I can't find such words in the GICv3/4 spec. :-)

See 1.2.3 "Models for handling interrupts" and the pointers this
section contains. The major difference is that 1:N is enabled on a
per-CPU basis instead of a per interrupt basis. Needless to say, Linux
doesn't support this, although I've been pondering it at times.

	M.

-- 
Without deviation from the norm, progress is not possible.


  reply	other threads:[~2024-09-10  7:39 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-04 20:23 [PATCH] irqchip/gic: prevent buffer overflow in gic_ipi_send_mask() Sergey Shtylyov
2024-09-05  7:29 ` Thomas Gleixner
2024-09-05  7:47   ` Marc Zyngier
2024-09-06 20:29     ` Sergey Shtylyov
2024-09-06 20:36       ` Sergey Shtylyov
2024-09-08  9:37       ` Marc Zyngier
2024-09-09 19:48         ` Sergey Shtylyov
2024-09-10  7:38           ` Marc Zyngier [this message]
2024-09-09 19:23   ` Sergey Shtylyov
2024-09-10  7:50     ` Marc Zyngier

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