From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B083CDB474 for ; Mon, 23 Oct 2023 12:31:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wpkG7QVs4pJkmoHQb0TYTqVsJTgvmcqbCQOrh7yqV2E=; b=pifXHxblI2S5ls StE6Z7nNGJbUzUnukbJugbMG1ajvd+kf/dJLlwCfl0WpbBkL7X1dFOOi+WzNFYvBVinCopEba25A7 AXFEWusULP4a1dudmDpsFA1Lc3Mkrhc94pn/j7PCXcolXrjEXrb44RCBnp/XAsX2Zjp4v0gGXg4ci mZbPxjmbryWXmb2wZl/Uk4p0PO8o+OiayD88QZozMqdIFtM6JDDuR1YZpBRCF2E+MQnhwO0bEf6X3 QPbDg48i3zoKjernVXOmUTms3hPtT1zTyT3Lj7K98K1GeExb43UMtbMIvl92PGY8JwsToy0ZNNGIU Bq0bc6zvvwh87NPHFKOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1quu5e-007Lzv-1i; Mon, 23 Oct 2023 12:31:26 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1quu5b-007Lz2-2p for linux-arm-kernel@lists.infradead.org; Mon, 23 Oct 2023 12:31:25 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id F0EA26249D; Mon, 23 Oct 2023 12:31:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 80F5CC433C7; Mon, 23 Oct 2023 12:31:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698064280; bh=vqvwI154cshBBrMmUKheC5NCWQ1/ynR+UUV9qp6rkWs=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=sV+BPrw7l9ZhjUGycj3+FYdcbY68ckuSY7HLf1EVSUhRtd99ldUqoBawO4+QzZJgm QhRrVUpePvLrb69JIVagjnGuMgJ+PEMVeoYH8Hfiux/b+qR2/yOmMAcDfrawH40+kz fuj5FzsfODCV+CFLn9IdrFaDcA9lwFQUPO+h74EuaSv/q+am1Bz48hOwrx69HMCveb OARvfJhlnfqvSqVMlFoGgEqlAkXi20V3wKiYV1BkFQ4ryiv5dRelvcjQmFiEY02q2I 6yazLzhr4EgoV83KazEcHAOJX+CjnJWz2K3HK97W/zlwJ8M/ZTVErMey7aWCQd/64z lDLb9ppYc0Q5Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1quu5W-006q35-25; Mon, 23 Oct 2023 13:31:18 +0100 Date: Mon, 23 Oct 2023 13:31:15 +0100 Message-ID: <86zg094j1o.wl-maz@kernel.org> From: Marc Zyngier To: Raghavendra Rao Ananta Cc: Oliver Upton , Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v8 05/13] KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} In-Reply-To: <20231020214053.2144305-6-rananta@google.com> References: <20231020214053.2144305-1-rananta@google.com> <20231020214053.2144305-6-rananta@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rananta@google.com, oliver.upton@linux.dev, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, yuzenghui@huawei.com, shahuang@redhat.com, jingzhangos@google.com, reijiw@google.com, coltonlewis@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231023_053124_004137_F58C18BC X-CRM114-Status: GOOD ( 26.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 20 Oct 2023 22:40:45 +0100, Raghavendra Rao Ananta wrote: > > For unimplemented counters, the bits in PM{C,I}NTEN{SET,CLR} and > PMOVS{SET,CLR} registers are expected to RAZ. To honor this, > explicitly implement the {get,set}_user functions for these > registers to mask out unimplemented counters for userspace reads > and writes. > > Signed-off-by: Raghavendra Rao Ananta > --- > arch/arm64/kvm/sys_regs.c | 91 ++++++++++++++++++++++++++++++++++++--- > 1 file changed, 85 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index faf97878dfbbb..2e5d497596ef8 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -987,6 +987,45 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu, > + u64 reg, u64 val, bool set) > +{ > + struct kvm *kvm = vcpu->kvm; > + > + mutex_lock(&kvm->arch.config_lock); > + > + /* Make the register immutable once the VM has started running */ > + if (kvm_vm_has_ran_once(kvm)) { > + mutex_unlock(&kvm->arch.config_lock); > + return; > + } > + > + val &= kvm_pmu_valid_counter_mask(vcpu); > + mutex_unlock(&kvm->arch.config_lock); > + > + if (set) > + __vcpu_sys_reg(vcpu, reg) |= val; > + else > + __vcpu_sys_reg(vcpu, reg) &= ~val; > +} > + > +static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, > + u64 *val) > +{ > + u64 mask = kvm_pmu_valid_counter_mask(vcpu); > + > + *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; > + return 0; > +} > + > +static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, > + u64 val) > +{ > + /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */ > + set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1); > + return 0; > +} Huh, this is really ugly. Why the explosion of pointless helpers when the whole design of the sysreg infrastructure to have *common* helpers for registers that behave the same way? I'd expect something like the hack below instead. M. diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a2c5f210b3d6..8f560a2496f2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -987,42 +987,46 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } -static void set_pmreg_for_valid_counters(struct kvm_vcpu *vcpu, - u64 reg, u64 val, bool set) +static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) { struct kvm *kvm = vcpu->kvm; + bool set; mutex_lock(&kvm->arch.config_lock); /* Make the register immutable once the VM has started running */ if (kvm_vm_has_ran_once(kvm)) { mutex_unlock(&kvm->arch.config_lock); - return; + return 0; } val &= kvm_pmu_valid_counter_mask(vcpu); mutex_unlock(&kvm->arch.config_lock); + switch(r->reg) { + case PMOVSSET_EL0: + /* CRm[1] being set indicates a SET register, and CLR otherwise */ + set = r->CRm & 2; + break; + default: + /* Op2[0] being set indicates a SET register, and CLR otherwise */ + set = r->Op2 & 1; + break; + } + if (set) - __vcpu_sys_reg(vcpu, reg) |= val; + __vcpu_sys_reg(vcpu, r->reg) |= val; else - __vcpu_sys_reg(vcpu, reg) &= ~val; -} - -static int get_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 *val) -{ - u64 mask = kvm_pmu_valid_counter_mask(vcpu); + __vcpu_sys_reg(vcpu, r->reg) &= ~val; - *val = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; return 0; } -static int set_pmcnten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 val) +static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) { - /* r->Op2 & 0x1: true for PMCNTENSET_EL0, else PMCNTENCLR_EL0 */ - set_pmreg_for_valid_counters(vcpu, PMCNTENSET_EL0, val, r->Op2 & 0x1); + u64 mask = kvm_pmu_valid_counter_mask(vcpu); + + *val = __vcpu_sys_reg(vcpu, r->reg) & mask; return 0; } @@ -1054,23 +1058,6 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } -static int get_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 *val) -{ - u64 mask = kvm_pmu_valid_counter_mask(vcpu); - - *val = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; - return 0; -} - -static int set_pminten(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 val) -{ - /* r->Op2 & 0x1: true for PMINTENSET_EL1, else PMINTENCLR_EL1 */ - set_pmreg_for_valid_counters(vcpu, PMINTENSET_EL1, val, r->Op2 & 0x1); - return 0; -} - static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1095,23 +1082,6 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } -static int set_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 val) -{ - /* r->CRm & 0x2: true for PMOVSSET_EL0, else PMOVSCLR_EL0 */ - set_pmreg_for_valid_counters(vcpu, PMOVSSET_EL0, val, r->CRm & 0x2); - return 0; -} - -static int get_pmovs(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, - u64 *val) -{ - u64 mask = kvm_pmu_valid_counter_mask(vcpu); - - *val = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; - return 0; -} - static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -2311,10 +2281,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { { PMU_SYS_REG(PMINTENSET_EL1), .access = access_pminten, .reg = PMINTENSET_EL1, - .get_user = get_pminten, .set_user = set_pminten }, + .get_user = get_pmreg, .set_user = set_pmreg }, { PMU_SYS_REG(PMINTENCLR_EL1), .access = access_pminten, .reg = PMINTENSET_EL1, - .get_user = get_pminten, .set_user = set_pminten }, + .get_user = get_pmreg, .set_user = set_pmreg }, { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, @@ -2366,13 +2336,13 @@ static const struct sys_reg_desc sys_reg_descs[] = { .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, { PMU_SYS_REG(PMCNTENSET_EL0), .access = access_pmcnten, .reg = PMCNTENSET_EL0, - .get_user = get_pmcnten, .set_user = set_pmcnten }, + .get_user = get_pmreg, .set_user = set_pmreg }, { PMU_SYS_REG(PMCNTENCLR_EL0), .access = access_pmcnten, .reg = PMCNTENSET_EL0, - .get_user = get_pmcnten, .set_user = set_pmcnten }, + .get_user = get_pmreg, .set_user = set_pmreg }, { PMU_SYS_REG(PMOVSCLR_EL0), .access = access_pmovs, .reg = PMOVSSET_EL0, - .get_user = get_pmovs, .set_user = set_pmovs }, + .get_user = get_pmreg, .set_user = set_pmreg }, /* * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was * previously (and pointlessly) advertised in the past... @@ -2401,7 +2371,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, { PMU_SYS_REG(PMOVSSET_EL0), .access = access_pmovs, .reg = PMOVSSET_EL0, - .get_user = get_pmovs, .set_user = set_pmovs }, + .get_user = get_pmreg, .set_user = set_pmreg }, { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel