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Sun, 29 Dec 2019 15:17:43 +0000 Date: Sun, 29 Dec 2019 15:17:40 +0000 Message-ID: <86zhfbgnzf.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH 1/3] KVM: arm64: correct PSTATE on exception entry In-Reply-To: References: <20191220150549.31948-1-mark.rutland@arm.com> <20191220150549.31948-2-mark.rutland@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, mark.rutland@arm.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, drjones@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, peter.maydell@linaro.org, suzuki.poulose@arm.com, will@kernel.org, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191229_071747_702880_BB68E853 X-CRM114-Status: GOOD ( 27.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Peter Maydell , Drew Jones , Suzuki K Poulose , stable@vger.kernel.org, James Morse , linux-arm-kernel@lists.infradead.org, Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 27 Dec 2019 13:01:57 +0000, Alexandru Elisei wrote: > > Hi, > > On 12/20/19 3:05 PM, Mark Rutland wrote: > > When KVM injects an exception into a guest, it generates the PSTATE > > value from scratch, configuring PSTATE.{M[4:0],DAIF}, and setting all > > other bits to zero. > > > > This isn't correct, as the architecture specifies that some PSTATE bits > > are (conditionally) cleared or set upon an exception, and others are > > unchanged from the original context. > > > > This patch adds logic to match the architectural behaviour. To make this > > simple to follow/audit/extend, documentation references are provided, > > and bits are configured in order of their layout in SPSR_EL2. This > > layout can be seen in the diagram on ARM DDI 0487E.a page C5-429. > > > > Signed-off-by: Mark Rutland > > Cc: Alexandru Elisei > > Cc: Drew Jones > > Cc: James Morse > > Cc: Julien Thierry > > Cc: Marc Zyngier > > Cc: Peter Maydell > > Cc: Suzuki K Poulose > > Cc: Will Deacon > > Cc: stable@vger.kernel.org > > --- > > arch/arm64/include/uapi/asm/ptrace.h | 1 + > > arch/arm64/kvm/inject_fault.c | 69 +++++++++++++++++++++++++++++++++--- > > 2 files changed, 65 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h > > index 7ed9294e2004..d1bb5b69f1ce 100644 > > --- a/arch/arm64/include/uapi/asm/ptrace.h > > +++ b/arch/arm64/include/uapi/asm/ptrace.h > > @@ -49,6 +49,7 @@ > > #define PSR_SSBS_BIT 0x00001000 > > #define PSR_PAN_BIT 0x00400000 > > #define PSR_UAO_BIT 0x00800000 > > +#define PSR_DIT_BIT 0x01000000 > > #define PSR_V_BIT 0x10000000 > > #define PSR_C_BIT 0x20000000 > > #define PSR_Z_BIT 0x40000000 > > diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c > > index a9d25a305af5..270d91c05246 100644 > > --- a/arch/arm64/kvm/inject_fault.c > > +++ b/arch/arm64/kvm/inject_fault.c > > @@ -14,9 +14,6 @@ > > #include > > #include > > > > -#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \ > > - PSR_I_BIT | PSR_D_BIT) > > - > > #define CURRENT_EL_SP_EL0_VECTOR 0x0 > > #define CURRENT_EL_SP_ELx_VECTOR 0x200 > > #define LOWER_EL_AArch64_VECTOR 0x400 > > @@ -50,6 +47,68 @@ static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type) > > return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type; > > } > > > > +/* > > + * When an exception is taken, most PSTATE fields are left unchanged in the > > + * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all > > + * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx > > + * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0. > > + * > > + * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. > > + * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. > > The commit message mentions only the SPSR_ELx layout for AArch64. > > > + * > > + * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from > > + * MSB to LSB. > > + */ > > +static unsigned long get_except64_pstate(struct kvm_vcpu *vcpu) > > +{ > > + unsigned long sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); > > + unsigned long old, new; > > + > > + old = *vcpu_cpsr(vcpu); > > + new = 0; > > + > > + new |= (old & PSR_N_BIT); > > + new |= (old & PSR_Z_BIT); > > + new |= (old & PSR_C_BIT); > > + new |= (old & PSR_V_BIT); > > + > > + // TODO: TCO (if/when ARMv8.5-MemTag is exposed to guests) > > + > > + new |= (old & PSR_DIT_BIT); > > + > > + // PSTATE.UAO is set to zero upon any exception to AArch64 > > + // See ARM DDI 0487E.a, page D5-2579. > > + > > + // PSTATE.PAN is unchanged unless overridden by SCTLR_ELx.SPAN > > + // See ARM DDI 0487E.a, page D5-2578. > > + new |= (old & PSR_PAN_BIT); > > + if (sctlr & SCTLR_EL1_SPAN) > > + new |= PSR_PAN_BIT; > > On page D13-3264, it is stated that the PAN bit is set unconditionally if > SCTLR_EL1.SPAN is clear, not set. Indeed. Given that when ARMv8.1-PAN is not implemented, SCTLR_EL1[23] is RES1, it seems surprising to force PAN based on this bit being set. I've now dropped this series from my tree until Mark has a chance to clarify this. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel