* [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers @ 2017-06-21 21:45 Marc Zyngier 2017-06-23 12:45 ` Gregory CLEMENT 0 siblings, 1 reply; 4+ messages in thread From: Marc Zyngier @ 2017-06-21 21:45 UTC (permalink / raw) To: linux-arm-kernel Contrary to popular belief, PPIs connected to a GICv3 to not have an affinity field similar to that of GICv2. That is consistent with the fact that GICv3 is designed to accomodate thousands of CPUs, and fitting them as a bitmap in a byte is... difficult. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 4d495ec39202..bc179efb10ef 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -75,14 +75,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; soc { -- 2.11.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers 2017-06-21 21:45 [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers Marc Zyngier @ 2017-06-23 12:45 ` Gregory CLEMENT 2017-07-03 13:35 ` Gregory CLEMENT 0 siblings, 1 reply; 4+ messages in thread From: Gregory CLEMENT @ 2017-06-23 12:45 UTC (permalink / raw) To: linux-arm-kernel Hi Marc, On mer., juin 21 2017, Marc Zyngier <marc.zyngier@arm.com> wrote: > Contrary to popular belief, PPIs connected to a GICv3 to not have > an affinity field similar to that of GICv2. That is consistent > with the fact that GICv3 is designed to accomodate thousands of > CPUs, and fitting them as a bitmap in a byte is... difficult. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Applied on mvebu/fixes Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- > 1 file changed, 4 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > index 4d495ec39202..bc179efb10ef 100644 > --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi > @@ -75,14 +75,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 > - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > - <GIC_PPI 14 > - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > - <GIC_PPI 11 > - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > - <GIC_PPI 10 > - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > }; > > soc { > -- > 2.11.0 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers 2017-06-23 12:45 ` Gregory CLEMENT @ 2017-07-03 13:35 ` Gregory CLEMENT 2017-07-03 16:21 ` Marc Zyngier 0 siblings, 1 reply; 4+ messages in thread From: Gregory CLEMENT @ 2017-07-03 13:35 UTC (permalink / raw) To: linux-arm-kernel Hi, On ven., juin 23 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote: > Hi Marc, > > On mer., juin 21 2017, Marc Zyngier <marc.zyngier@arm.com> wrote: > >> Contrary to popular belief, PPIs connected to a GICv3 to not have >> an affinity field similar to that of GICv2. That is consistent >> with the fact that GICv3 is designed to accomodate thousands of >> CPUs, and fitting them as a bitmap in a byte is... difficult. >> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > > Applied on mvebu/fixes As I missed the end of the merge window for 4.12, I've just moved this patch on mvebu/dt64 wit the hope that it can be applied on a late dt branch on arm-soc for 4.13. I also added the "Fixes" and "CC: stable" tags in order to propagate the fix on older kernel. Gregory > >> --- >> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 12 ++++-------- >> 1 file changed, 4 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi >> index 4d495ec39202..bc179efb10ef 100644 >> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi >> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi >> @@ -75,14 +75,10 @@ >> >> timer { >> compatible = "arm,armv8-timer"; >> - interrupts = <GIC_PPI 13 >> - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> - <GIC_PPI 14 >> - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> - <GIC_PPI 11 >> - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> - <GIC_PPI 10 >> - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> soc { >> -- >> 2.11.0 >> > > -- > Gregory Clement, Free Electrons > Kernel, drivers, real-time and embedded Linux > development, consulting, training and support. > http://free-electrons.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers 2017-07-03 13:35 ` Gregory CLEMENT @ 2017-07-03 16:21 ` Marc Zyngier 0 siblings, 0 replies; 4+ messages in thread From: Marc Zyngier @ 2017-07-03 16:21 UTC (permalink / raw) To: linux-arm-kernel Hi Gregory, On 03/07/17 14:35, Gregory CLEMENT wrote: > Hi, > > On ven., juin 23 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote: > >> Hi Marc, >> >> On mer., juin 21 2017, Marc Zyngier <marc.zyngier@arm.com> wrote: >> >>> Contrary to popular belief, PPIs connected to a GICv3 to not have >>> an affinity field similar to that of GICv2. That is consistent >>> with the fact that GICv3 is designed to accomodate thousands of >>> CPUs, and fitting them as a bitmap in a byte is... difficult. >>> >>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> >> Applied on mvebu/fixes > > As I missed the end of the merge window for 4.12, I've just moved this > patch on mvebu/dt64 wit the hope that it can be applied on a late dt > branch on arm-soc for 4.13. > > I also added the "Fixes" and "CC: stable" tags in order to propagate the > fix on older kernel. While you're at it, you could also add the couple of GIC-related fixes I've posted on Saturday (which are equally important). Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-07-03 16:21 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-06-21 21:45 [PATCH] ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers Marc Zyngier 2017-06-23 12:45 ` Gregory CLEMENT 2017-07-03 13:35 ` Gregory CLEMENT 2017-07-03 16:21 ` Marc Zyngier
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).