From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BEA0C48260 for ; Fri, 16 Feb 2024 21:04:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=knv3pzjGF1B5v3TBWyXiEMhUAko0gE/+ppXoAQXRyUc=; b=rH5Ajz7SHZsBGc zc52aihAOUXd+ULdF/DSpRAjRE4y2NuXPkQSrxom1tEWpVSHdVe5lZ/MFK8rVwQfTXUvrtUf4ltd/ yJlBfITLO+vu41TtK9s9PLpTkgtgzIRPQN3ISz7VHGYVXrxRmniUKUAT/rh1AMD3iDNmAPyCsgsB2 R3UkI8LPc0oYv7RzGsIxEBPHeIV7BzjRBtP80mVWQ++NR039Af8OE1QRRYatJ6pYs87NwSGjxPosb r/9SCpAvaQefZh983pnfrlFXiW7Y/yt0RhOPqTbVkYJIvQ3fPYmgOtqslw1ZBpyfFJnWxYutGkkQI 72sXpQoc67LYcPmT2jZQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rb5NT-00000003kj5-2rCD; Fri, 16 Feb 2024 21:04:11 +0000 Received: from galois.linutronix.de ([193.142.43.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rb5NN-00000003khQ-3K6I; Fri, 16 Feb 2024 21:04:09 +0000 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708117444; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=aPil28lXVu/5EuMTMJHAF2NuE7S20nDRKRUxcPw2x9A=; b=09tYLByROgD3bDLYAoILh20drVnloPdm8qHaCVHSa8YslAkk+vHe5GCMRqEPgmXapRXwp7 haMLpBFhy7xqoxZcqtyf08Ob2ZjGCB9hHnx50L0qLeyomv7uwZvRwLH5+eCY0q2Kl3SlS8 wMobBVNcDkGtumiuGA36kP32BR/n7Od+jQT19U9Hk6sC/MdjnDn31ojtc+Xf3o707kLWlw hJHDBj443oH4lxAbBirQ48SRQP4as2LG7Q3yN3yRzLeFpVFJFq5MfBoxZW7EXofWFsaCyK Owe5hwIfmeW55ddNzU4jbNTyfHMS0Z8JV9K5LFqZln4wBoUDprmPjYu1DfgFbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708117444; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=aPil28lXVu/5EuMTMJHAF2NuE7S20nDRKRUxcPw2x9A=; b=sTHsysm3f+56VNyke1nWTeQXTpJX/RT7U3ejiMXUtOjW65iwO9Uv6f1hJoBVOWapBEc/Mk 3esMRQST3WxV1PBg== To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: Re: [PATCH v12 23/25] irqchip/riscv-aplic: Add support for MSI-mode In-Reply-To: <20240127161753.114685-24-apatel@ventanamicro.com> References: <20240127161753.114685-1-apatel@ventanamicro.com> <20240127161753.114685-24-apatel@ventanamicro.com> Date: Fri, 16 Feb 2024 22:04:03 +0100 Message-ID: <8734tsce9o.ffs@tglx> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240216_130406_015308_7A1A45D4 X-CRM114-Status: GOOD ( 10.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Jan 27 2024 at 21:47, Anup Patel wrote: > We extend the existing APLIC irqchip driver to support MSI-mode for > RISC-V platforms having both wired interrupts and MSIs. We? Just s/We// > + > +static void aplic_msi_irq_unmask(struct irq_data *d) > +{ > + aplic_irq_unmask(d); > + irq_chip_unmask_parent(d); > +} > + > +static void aplic_msi_irq_mask(struct irq_data *d) > +{ > + aplic_irq_mask(d); > + irq_chip_mask_parent(d); > +} Again asymmetric vs. unmask() > +static void aplic_msi_irq_eoi(struct irq_data *d) > +{ > + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); > + u32 reg_off, reg_mask; > + > + /* > + * EOI handling only required only for level-triggered > + * interrupts in APLIC MSI mode. > + */ > + > + reg_off = APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4); > + reg_mask = BIT(d->hwirq % APLIC_IRQBITS_PER_REG); > + switch (irqd_get_trigger_type(d)) { > + case IRQ_TYPE_LEVEL_LOW: > + if (!(readl(priv->regs + reg_off) & reg_mask)) > + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); A comment what this condition is for would be nice. Thanks, tglx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel