Re: [PATCH v3] KVM: arm64: Use BTI for nvhe

From: Marc Zyngier <maz@kernel.org>
To: Mostafa Saleh <smostafa@google.com>
Cc: oliver.upton@linux.dev, Sudeep Holla <sudeep.holla@arm.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-kernel@vger.kernel.org, tabba@google.com,
	qperret@google.com, will@kernel.org, catalin.marinas@arm.com,
	yuzenghui@huawei.com, suzuki.poulose@arm.com,
	james.morse@arm.com, bgardon@google.com, gshan@redhat.com
Subject: Re: [PATCH v3] KVM: arm64: Use BTI for nvhe
Date: Thu, 06 Jul 2023 15:27:36 +0100	[thread overview]
Message-ID: <873521yv1j.wl-maz@kernel.org> (raw)
In-Reply-To: <CAFgf54rQmBMgvRWj2yqQ90=12x-Tm1BkHj_-pf+ZBYPmBU_Swg@mail.gmail.com>

Hi Mostafa,

On Thu, 06 Jul 2023 13:49:04 +0100,
Mostafa Saleh <smostafa@google.com> wrote:
> 
> Hi Marc and Oliver,
> 
> I was double checking that nothing else was missed.
> 
> I found there is another problem for hw that has BTI and is affected
> by specterv3a.
> 
> "br'' instructions are generated at runtime for the vector
> table(__bp_harden_hyp_vecs).  These branches would land on vectors
> in __kvm_hyp_vector at offset 8.
> 
> As all the macros are defined with valid_vect/invalid_vect, it is
> sufficient to add "bti j" there at the correct offset.
>
> I am not sure if such hardware exists. I tested this with a stubbed
> "has_spectre_v3a" which confirms the issue and the fix.

Thanks for the heads up.

Fortunately, there is no such HW as far as I can tell. Only Cortex-A57
and A72 are affected by this (and the only two CPUs for which we
engage the mitigation), and they are way too old to know about BTI.

> Please let me know if this fix suitable, I can include it with the other fix in
> "[PATCH] KVM: arm64: Add missing BTI instruction in kvm_host_psci_cpu_entry"
> 
> diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S
> index 8f3f93fa119e..175c030379e3 100644
> --- a/arch/arm64/kvm/hyp/hyp-entry.S
> +++ b/arch/arm64/kvm/hyp/hyp-entry.S
> @@ -154,6 +154,12 @@ SYM_CODE_END(\label)
>   esb
>   stp x0, x1, [sp, #-16]!
>  662:
> + /*
> + * Specter vectors __bp_harden_hyp_vecs generate br instructions at runtime
> + * that jump at offset 8 at __kvm_hyp_vector.
> + * As hyp .text is guarded section, it needs bti j.
> + */
> + bti j
>   b \target
> 
>  check_preamble_length 661b, 662b
> @@ -165,6 +171,8 @@ check_preamble_length 661b, 662b
>   nop
>   stp x0, x1, [sp, #-16]!
>  662:
> + /* Check valid_vect */
> + bti j
>   b \target
> 
>  check_preamble_length 661b, 662b

This looks correct to me.

If you can respin you initial patch (with maybe a slightly more
generic subject) so that Oliver can pick it up as part of the next
batch of fixes, that'd be great.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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