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Sun, 12 Sep 2021 21:46:51 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mPVr2-00H8St-Hm; Sun, 12 Sep 2021 20:13:34 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D1C4E610FD; Sun, 12 Sep 2021 20:13:31 +0000 (UTC) Received: from [198.52.44.129] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mPVqy-00AKO5-6y; Sun, 12 Sep 2021 21:13:28 +0100 Date: Sun, 12 Sep 2021 21:13:17 +0100 Message-ID: <8735q9d02q.wl-maz@kernel.org> From: Marc Zyngier To: Mark Kettenis Cc: Rob Herring , devicetree@vger.kernel.org, alyssa@rosenzweig.io, kettenis@openbsd.org, tglx@linutronix.de, marcan@marcan.st, bhelgaas@google.com, jim2101024@gmail.com, nsaenz@kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, daire.mcnamara@microchip.com, nsaenzjulienne@suse.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: Re: [PATCH v4 3/4] dt-bindings: pci: Add DT bindings for apple,pcie In-Reply-To: <561431b178447575@bloch.sibelius.xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> <20210827171534.62380-4-mark.kettenis@xs4all.nl> <561431b178447575@bloch.sibelius.xs4all.nl> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 198.52.44.129 X-SA-Exim-Rcpt-To: mark.kettenis@xs4all.nl, robh@kernel.org, devicetree@vger.kernel.org, alyssa@rosenzweig.io, kettenis@openbsd.org, tglx@linutronix.de, marcan@marcan.st, bhelgaas@google.com, jim2101024@gmail.com, nsaenz@kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, daire.mcnamara@microchip.com, nsaenzjulienne@suse.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210912_131332_711192_A4EE74D2 X-CRM114-Status: GOOD ( 38.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 01 Sep 2021 12:29:22 +0100, Mark Kettenis wrote: > > > Date: Tue, 31 Aug 2021 16:21:28 -0500 > > From: Rob Herring > > > > On Fri, Aug 27, 2021 at 07:15:28PM +0200, Mark Kettenis wrote: > > > From: Mark Kettenis > > > > > > The Apple PCIe host controller is a PCIe host controller with > > > multiple root ports present in Apple ARM SoC platforms, including > > > various iPhone and iPad devices and the "Apple Silicon" Macs. > > > > > > Signed-off-by: Mark Kettenis > > > --- > > > .../devicetree/bindings/pci/apple,pcie.yaml | 165 ++++++++++++++++++ > > > MAINTAINERS | 1 + > > > 2 files changed, 166 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml > > > new file mode 100644 > > > index 000000000000..97a126db935a > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml > > > @@ -0,0 +1,165 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Apple PCIe host controller > > > + > > > +maintainers: > > > + - Mark Kettenis > > > + > > > +description: | > > > + The Apple PCIe host controller is a PCIe host controller with > > > + multiple root ports present in Apple ARM SoC platforms, including > > > + various iPhone and iPad devices and the "Apple Silicon" Macs. > > > + The controller incorporates Synopsys DesigWare PCIe logic to > > > + implements its root ports. But the ATU found on most DesignWare > > > + PCIe host bridges is absent. > > > + > > > + All root ports share a single ECAM space, but separate GPIOs are > > > + used to take the PCI devices on those ports out of reset. Therefore > > > + the standard "reset-gpios" and "max-link-speed" properties appear on > > > + the child nodes that represent the PCI bridges that correspond to > > > + the individual root ports. > > > + > > > + MSIs are handled by the PCIe controller and translated into regular > > > + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be > > > + distributed over the root ports as the OS sees fit by programming > > > + the PCIe controller's port registers. > > > + > > > +allOf: > > > + - $ref: /schemas/pci/pci-bus.yaml# > > > + - $ref: ../interrupt-controller/msi-controller.yaml# > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - const: apple,t8103-pcie > > > + - const: apple,pcie > > > + > > > + reg: > > > + minItems: 3 > > > + maxItems: 5 > > > + > > > + reg-names: > > > + minItems: 3 > > > + maxItems: 5 > > > + items: > > > + - const: config > > > + - const: rc > > > + - const: port0 > > > + - const: port1 > > > + - const: port2 > > > + > > > + ranges: > > > + minItems: 2 > > > + maxItems: 2 > > > + > > > + interrupts: > > > + description: > > > + Interrupt specifiers, one for each root port. > > > + minItems: 1 > > > + maxItems: 3 > > > + > > > + msi-parent: true > > > > I still think this should be dropped as it is meaningless with > > 'msi-controller' present. > > Hmm. As far as I can tell all current arm64 device trees that > describe hardware with an MSI controller integrated on the PCI host > bridge have both the 'msi-controller' and 'msi-parent' properties. > See arch/arm64/boot/dts/marvell/aramada-37xx.dtsi and > arch/arm64/boot/dts/xilinx/zynqmp.dtsi. > > The current OpenBSD code will fail to map the MSIs if 'msi-parent' > isn't there, although Linux seems to fall back on an MSI domain that's > directly attached to the host bridge if the 'msi-parent' property is > missing. I think it makes sense to be explicit here, but if both you > and Marc think it shouldn't be there, I probably can change the > OpenBSD to do a similar fallback. I think this matches the behaviour we have for interrupt-controller vs interrupt-parent. I fail to see why msi-controller/msi-parent should behave differently. And since there is an established OS that actually requires this, I don't see how we can today make it illegal. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel