[PATCH 0/6] Add the registers clock for most of the peripherals

[PATCH 0/6] Add the registers clock for most of the peripherals

[Gregory CLEMENT]

Hi,

Thanks to new documentation, we have a better view of the clock
tree. It made us realized that most of the peripherals needs a second
clock to enable their registers.

Now that most of the binding change had been applied or are in the way
to be applied, we can update the device tree.

Gregory

Gregory CLEMENT (6):
  ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
    nodes
  ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
    nodes
  ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
    node
  ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
    node
  ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
    node
  ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
    nodes

 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
 1 file changed, 27 insertions(+), 10 deletions(-)

-- 
2.16.1

[PATCH 1/6] ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes

[Gregory CLEMENT]

This extra clock is needed to access the registers of the USB host
controller used on Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "usb: host: xhci-plat: Fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 355bb295e4d9..c35368d2a4cd 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -211,7 +211,9 @@
 			reg = <0x500000 0x4000>;
 			dma-coherent;
 			interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 22>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 22>,
+				 <&CP110_LABEL(clk) 1 16>;
 			status = "disabled";
 		};
 
@@ -221,7 +223,9 @@
 			reg = <0x510000 0x4000>;
 			dma-coherent;
 			interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 23>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 23>,
+				 <&CP110_LABEL(clk) 1 16>;
 			status = "disabled";
 		};
 
-- 
2.16.1

[PATCH 2/6] ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes

[Gregory CLEMENT]

This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index c35368d2a4cd..a51c553b5120 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -244,7 +244,9 @@
 			reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
 			dma-coherent;
 			msi-parent = <&gic_v2m0>;
-			clocks = <&CP110_LABEL(clk) 1 8>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 8>,
+				 <&CP110_LABEL(clk) 1 14>;
 		};
 
 		CP110_LABEL(xor1): xor at 6c0000 {
@@ -252,7 +254,9 @@
 			reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
 			dma-coherent;
 			msi-parent = <&gic_v2m0>;
-			clocks = <&CP110_LABEL(clk) 1 7>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 7>,
+				 <&CP110_LABEL(clk) 1 14>;
 		};
 
 		CP110_LABEL(spi0): spi at 700600 {
-- 
2.16.1

[PATCH 3/6] ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node

[Gregory CLEMENT]

This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "hwrng: omap - Fix clock resource by adding a
register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index a51c553b5120..c491adc90b8c 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -375,7 +375,9 @@
 			"inside-secure,safexcel-eip76";
 			reg = <0x760000 0x7d>;
 			interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 25>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 25>,
+				 <&CP110_LABEL(clk) 1 17>;
 			status = "okay";
 		};
 
-- 
2.16.1

[PATCH 4/6] ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node

[Gregory CLEMENT]

This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "crypto: inside-secure - fix clock resource by
adding a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index c491adc90b8c..b6947fcb8ce6 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -402,7 +402,9 @@
 				<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mem", "ring0", "ring1",
 				"ring2", "ring3", "eip";
-			clocks = <&CP110_LABEL(clk) 1 26>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 26>,
+				 <&CP110_LABEL(clk) 1 17>;
 			dma-coherent;
 		};
 	};
-- 
2.16.1

[PATCH 5/6] ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node

[Gregory CLEMENT]

This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "mtd: nand: marvell: Fix clock resource by adding
a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index b6947fcb8ce6..9ffb86b9441e 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -365,7 +365,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&CP110_LABEL(clk) 1 2>;
+			clock-names = "core", "reg";
+			clocks = <&CP110_LABEL(clk) 1 2>,
+				 <&CP110_LABEL(clk) 1 17>;
 			marvell,system-controller = <&CP110_LABEL(syscon0)>;
 			status = "disabled";
 		};
-- 
2.16.1

[PATCH 6/6] ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes

[Gregory CLEMENT]

This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 9ffb86b9441e..48cad7919efa 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -433,7 +433,8 @@
 		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 		interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 13>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};
 
@@ -460,7 +461,8 @@
 		interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 11>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};
 
@@ -487,7 +489,8 @@
 		interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 
 		num-lanes = <1>;
-		clocks = <&CP110_LABEL(clk) 1 12>;
+		clock-names = "core", "reg";
+		clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
 		status = "disabled";
 	};
 };
-- 
2.16.1

[PATCH 0/6] Add the registers clock for most of the peripherals

[Gregory CLEMENT]

Hi,
 
 On mer., mars 14 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:

> Hi,
>
> Thanks to new documentation, we have a better view of the clock
> tree. It made us realized that most of the peripherals needs a second
> clock to enable their registers.

I forgot to mention that this series was for the Armada 7K/8K SoCs from
Marvell!

>
> Now that most of the binding change had been applied or are in the way
> to be applied, we can update the device tree.
>
> Gregory
>
> Gregory CLEMENT (6):
>   ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
>     nodes
>   ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
>     nodes
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
>     nodes
>
>  arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
>  1 file changed, 27 insertions(+), 10 deletions(-)
>
> -- 
> 2.16.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

[PATCH 0/6] Add the registers clock for most of the peripherals

[Gregory CLEMENT]

Hi,

 On mer., mars 14 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:

> Hi,
>
> Thanks to new documentation, we have a better view of the clock
> tree. It made us realized that most of the peripherals needs a second
> clock to enable their registers.
>
> Now that most of the binding change had been applied or are in the way
> to be applied, we can update the device tree.
>

All series applied on mvebu/dt64,

Gregory

> Gregory
>
> Gregory CLEMENT (6):
>   ARM64: dts: marvell: armada-cp110: Add registers clock for USB host
>     nodes
>   ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine
>     nodes
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the trng
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND
>     node
>   ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe
>     nodes
>
>  arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 37 +++++++++++++++++++--------
>  1 file changed, 27 insertions(+), 10 deletions(-)
>
> -- 
> 2.16.1
>

-- 
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com