[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Vaibhav Hiremath]

This patch series adds support for AM335X basic voltage, power,
clock and HWMOD data to existing OMAP framework.
Care has been taken while adding new API's to make sure that
we don't duplicate the code, and API's being added only
wherever required (where we didn't had any option).

The main purpose of this patch-series is to get early feedback &
review comments from list.

NOTE: Also please note that, most of the files are auto-generated
using HW data base and then modified based on latest kernel changes &
bug fixes.

For further information on AM33XX family of devices, please
refer to below links,

Official website -
http://www.ti.com/product/am3359

Link to Public TRM -
http://www.ti.com/lit/ug/spruh73a/spruh73a.pdf

This patch series has beed created on top of linux-omap/master +
AM33XX baseport patches submitted previously.
Link to AM335X Baseport patches -

http://www.spinics.net/lists/linux-omap/msg60088.html
http://www.spinics.net/lists/linux-omap/msg60087.html
http://www.spinics.net/lists/linux-omap/msg60090.html
http://www.spinics.net/lists/linux-omap/msg60089.html

Testing -
	- These patches has been tested on OMAP3EVM to make sure
	 nothing has been broken.
	- Patches has also been tested on AM335X EVM
	(with few additional patches).
	- All the patches can be accessible from,
http://arago-project.org/git/people/?p=vaibhav/ti-psp-omap-video.git;a=summary am335x-staging

Afzal Mohammed (6):
  arm:omap:am33xx: Add voltage domain data
  arm:omap:am33xx: Integrate voltage domain
  arm:omap:am33xx: Add power domain data
  arm:omap:am33xx: Integrate powerdomain to OMAP power framework
  arm:omap:am33xx: Add Clock & clockdomain data
  arm:omap:am33xx: Integrate clock & clockdomain to OMAP clock
    framework

Vaibhav Hiremath (5):
  arm:omap:am33xx: Add irq, dma and module base addr to SoC header
    files
  arm:omap:am33xx: Add HWMOD data
  arm:omap:am33xx: Integrate AM33XX hwmods to omap HWMOD framework
  ARM:omap:am33xx: Add clock control api's
  arm:omap:am33xx: Add am335x support in generic omap_hwmod

 arch/arm/mach-omap2/Makefile                  |    9 +
 arch/arm/mach-omap2/clock33xx.c               |   82 +
 arch/arm/mach-omap2/clock33xx.h               |   40 +
 arch/arm/mach-omap2/clock33xx_data.c          | 1936 +++++++++++++++++++
 arch/arm/mach-omap2/clock3xxx_data.c          |    5 +-
 arch/arm/mach-omap2/clockdomain.h             |    1 +
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c    |   18 +-
 arch/arm/mach-omap2/clockdomains33xx_data.c   |  223 +++
 arch/arm/mach-omap2/cm-regbits-33xx.h         |  683 +++++++
 arch/arm/mach-omap2/cm2xxx_3xxx.c             |   34 +
 arch/arm/mach-omap2/cm2xxx_3xxx.h             |    6 +
 arch/arm/mach-omap2/cm33xx.c                  |   51 +
 arch/arm/mach-omap2/cm33xx.h                  |  390 ++++
 arch/arm/mach-omap2/cminst33xx.c              |  311 ++++
 arch/arm/mach-omap2/cminst33xx.h              |   63 +
 arch/arm/mach-omap2/io.c                      |    5 +
 arch/arm/mach-omap2/omap_hwmod.c              |   42 +-
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c    | 2474 +++++++++++++++++++++++++
 arch/arm/mach-omap2/powerdomain.h             |    4 +-
 arch/arm/mach-omap2/powerdomain33xx.c         |  155 ++
 arch/arm/mach-omap2/powerdomains33xx_data.c   |  115 ++
 arch/arm/mach-omap2/prm-regbits-33xx.h        |  357 ++++
 arch/arm/mach-omap2/prm33xx.h                 |  123 ++
 arch/arm/mach-omap2/prminst33xx.c             |   74 +
 arch/arm/mach-omap2/prminst33xx.h             |   25 +
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains33xx_data.c |   37 +
 arch/arm/plat-omap/include/plat/am33xx.h      |   40 +
 arch/arm/plat-omap/include/plat/dma-33xx.h    |   85 +
 arch/arm/plat-omap/include/plat/dma.h         |    1 +
 arch/arm/plat-omap/include/plat/irqs-33xx.h   |  143 ++
 arch/arm/plat-omap/include/plat/irqs.h        |    1 +
 arch/arm/plat-omap/include/plat/omap_hwmod.h  |    1 +
 arch/arm/plat-omap/include/plat/serial.h      |    5 +
 34 files changed, 7525 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clock33xx.c
 create mode 100644 arch/arm/mach-omap2/clock33xx.h
 create mode 100644 arch/arm/mach-omap2/clock33xx_data.c
 create mode 100644 arch/arm/mach-omap2/clockdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/cm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/cm33xx.c
 create mode 100644 arch/arm/mach-omap2/cm33xx.h
 create mode 100644 arch/arm/mach-omap2/cminst33xx.c
 create mode 100644 arch/arm/mach-omap2/cminst33xx.h
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.h
 create mode 100644 arch/arm/mach-omap2/prminst33xx.c
 create mode 100644 arch/arm/mach-omap2/prminst33xx.h
 create mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c
 create mode 100644 arch/arm/plat-omap/include/plat/dma-33xx.h
 create mode 100644 arch/arm/plat-omap/include/plat/irqs-33xx.h

[RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data

[Vaibhav Hiremath]

From: Afzal Mohammed <afzal@ti.com>

Currently dummy voltage domain data is being created
in order to succeed boot process.
Nothing has been done w.r.t actual hardware (voltage control).

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains33xx_data.c |   37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c

diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b09..a7c43c1 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);

 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
+extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);

 struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 0000000..f8c817a
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,37 @@
+/*
+ * AM33XX voltage domain data
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "voltage.h"
+
+static struct voltagedomain am33xx_voltdm_mpu = {
+	.name = "mpu",
+};
+
+static struct voltagedomain am33xx_voltdm_core = {
+	.name = "core",
+};
+
+static struct voltagedomain am33xx_voltdm_rtc = {
+	.name = "rtc",
+};
+
+static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
+	&am33xx_voltdm_mpu,
+	&am33xx_voltdm_core,
+	&am33xx_voltdm_rtc,
+	NULL,
+};
+
+void __init am33xx_voltagedomains_init(void)
+{
+	voltdm_init(voltagedomains_am33xx);
+}
--
1.7.0.4

[RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> From: Afzal Mohammed <afzal@ti.com>
>
> Currently dummy voltage domain data is being created
> in order to succeed boot process.
> Nothing has been done w.r.t actual hardware (voltage control).
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

[...]

> --- /dev/null
> +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
> @@ -0,0 +1,37 @@
> +/*
> + * AM33XX voltage domain data
> + *
> + * Copyright (C) 2011 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +
> +#include "voltage.h"
> +
> +static struct voltagedomain am33xx_voltdm_mpu = {
> +	.name = "mpu",
> +};

According to the TRM, there is no MPU voltage domain.  Only CORE and RTC
exist.  

However, looking at the data manual (SPRS717 Oct 2011), it seems that
some packages have a separate VDD_MPU while others have a combined
VDD_MPU and VDD_CORE.

This should be clarified and documented in the changelog.

> +static struct voltagedomain am33xx_voltdm_core = {
> +	.name = "core",
> +};
> +
> +static struct voltagedomain am33xx_voltdm_rtc = {
> +	.name = "rtc",
> +};

Won't these basically empty voltage domains fail during voltage init?
At a minimum, it seems they should have '.scaling = false' as well until
voltage scalling is supported.

> +static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
> +	&am33xx_voltdm_mpu,
> +	&am33xx_voltdm_core,
> +	&am33xx_voltdm_rtc,
> +	NULL,
> +};
> +
> +void __init am33xx_voltagedomains_init(void)
> +{
> +	voltdm_init(voltagedomains_am33xx);
> +}

Kevin

[RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 5:41 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal
> Subject: Re: [RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > From: Afzal Mohammed <afzal@ti.com>
> >
> > Currently dummy voltage domain data is being created
> > in order to succeed boot process.
> > Nothing has been done w.r.t actual hardware (voltage control).
> >
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> [...]
> 
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
> > @@ -0,0 +1,37 @@
> > +/*
> > + * AM33XX voltage domain data
> > + *
> > + * Copyright (C) 2011 Texas Instruments, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +
> > +#include "voltage.h"
> > +
> > +static struct voltagedomain am33xx_voltdm_mpu = {
> > +	.name = "mpu",
> > +};
> 
> According to the TRM, there is no MPU voltage domain.  Only CORE and RTC
> exist.
> 
> However, looking at the data manual (SPRS717 Oct 2011), it seems that
> some packages have a separate VDD_MPU while others have a combined
> VDD_MPU and VDD_CORE.
> 
> This should be clarified and documented in the changelog.
> 


No, we do have VDD_MPU specifically documented in TRM (SPRUH73 - October2011).

The TRM is accessible at - http://www.ti.com/lit/ug/spruh73/spruh73.pdf


> > +static struct voltagedomain am33xx_voltdm_core = {
> > +	.name = "core",
> > +};
> > +
> > +static struct voltagedomain am33xx_voltdm_rtc = {
> > +	.name = "rtc",
> > +};
> 
> Won't these basically empty voltage domains fail during voltage init?
> At a minimum, it seems they should have '.scaling = false' as well until
> voltage scalling is supported.
> 

It won't fail, but I agree to your point that we should clearly specify
the state here.
I will add ".scaling = false" in next version.

Thanks a ton for the review.

Thanks,
Vaibhav

> > +static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
> > +	&am33xx_voltdm_mpu,
> > +	&am33xx_voltdm_core,
> > +	&am33xx_voltdm_rtc,
> > +	NULL,
> > +};
> > +
> > +void __init am33xx_voltagedomains_init(void)
> > +{
> > +	voltdm_init(voltagedomains_am33xx);
> > +}
> 
> Kevin

[RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data

[Kevin Hilman]

"Hiremath, Vaibhav" <hvaibhav@ti.com> writes:

>> -----Original Message-----
>> From: Hilman, Kevin
>> Sent: Thursday, December 01, 2011 5:41 AM
>> To: Hiremath, Vaibhav
>> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
>> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal
>> Subject: Re: [RFC PATCH 01/11] arm:omap:am33xx: Add voltage domain data
>> 
>> Vaibhav Hiremath <hvaibhav@ti.com> writes:
>> 
>> > From: Afzal Mohammed <afzal@ti.com>
>> >
>> > Currently dummy voltage domain data is being created
>> > in order to succeed boot process.
>> > Nothing has been done w.r.t actual hardware (voltage control).
>> >
>> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
>> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
>> 
>> [...]
>> 
>> > --- /dev/null
>> > +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
>> > @@ -0,0 +1,37 @@
>> > +/*
>> > + * AM33XX voltage domain data
>> > + *
>> > + * Copyright (C) 2011 Texas Instruments, Inc.
>> > + *
>> > + * This program is free software; you can redistribute it and/or modify
>> > + * it under the terms of the GNU General Public License version 2 as
>> > + * published by the Free Software Foundation.
>> > + */
>> > +#include <linux/kernel.h>
>> > +#include <linux/init.h>
>> > +
>> > +#include "voltage.h"
>> > +
>> > +static struct voltagedomain am33xx_voltdm_mpu = {
>> > +	.name = "mpu",
>> > +};
>> 
>> According to the TRM, there is no MPU voltage domain.  Only CORE and RTC
>> exist.
>> 
>> However, looking at the data manual (SPRS717 Oct 2011), it seems that
>> some packages have a separate VDD_MPU while others have a combined
>> VDD_MPU and VDD_CORE.
>> 
>> This should be clarified and documented in the changelog.
>> 
>
>
> No, we do have VDD_MPU specifically documented in TRM (SPRUH73 - October2011).
>
> The TRM is accessible at - http://www.ti.com/lit/ug/spruh73/spruh73.pdf

That link doesn't work for me, I think you meant

     http://www.ti.com/lit/ug/spruh73a/spruh73a.pdf

which is the document I'm reading.  Specifically it says:

8.1.1.10 Voltage and Power Domains

The following table shows how the device core logic is partitioned into
two core logic voltage domains and four power domains. The table lists
which voltage and power domain a functional module belongs.

Table 8-25. Core Logic Voltage and Power Domains
      Logic Voltage Domain Name    |  Module
      ---------------------------------------------
      CORE                         |  All Core Modules
      RTC                          |  RTC

8.1.1.10.1 Voltage Domains

The core logic is divided into two voltage domains: VDD_CORE and
VDD_RTC.



However, in reading other parts of the TRM, it clearly references
VDD_MPU and the data manual also references a separate VDD_MPU.

My point in this comment was that since the TRM is rather unclear on
this, the changelog should be more verbose, and take care to clear up
any thing that's wrong or unclear in the TRM.

Kevin

[RFC PATCH 02/11] arm:omap:am33xx: Integrate voltage domain data

[Vaibhav Hiremath]

From: Afzal Mohammed <afzal@ti.com>

Hook up AM33XX voltage domain info to OMAP framework.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/Makefile |    2 ++
 arch/arm/mach-omap2/io.c     |    1 +
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b33a85f..d4a9a61 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -95,6 +95,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= $(voltagedomain-common) \
 					   voltagedomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common) \
 					   voltagedomains3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(voltagedomain-common) \
+					   voltagedomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common) \
 					   voltagedomains44xx_data.o

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e958c04..b67d2ca 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -465,6 +465,7 @@ void __init am33xx_init_early(void)
 {
 	omap2_set_globals_am33xx();
 	omap_common_init_early();
+	am33xx_voltagedomains_init();
 	omap3xxx_clk_init();
 }
 #endif
--
1.7.0.4

[RFC PATCH 02/11] arm:omap:am33xx: Integrate voltage domain data

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> From: Afzal Mohammed <afzal@ti.com>
>
> Hook up AM33XX voltage domain info to OMAP framework.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

Should be  part of previous patch.

Kevin

[RFC PATCH 02/11] arm:omap:am33xx: Integrate voltage domain data

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 5:43 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal
> Subject: Re: [RFC PATCH 02/11] arm:omap:am33xx: Integrate voltage domain
> data
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > From: Afzal Mohammed <afzal@ti.com>
> >
> > Hook up AM33XX voltage domain info to OMAP framework.
> >
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Should be  part of previous patch.
> 
Ok, will take care in next version.

Thanks,
Vaibhav


> Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Vaibhav Hiremath]

From: Afzal Mohammed <afzal@ti.com>

This patch adds AM33XX power domain data,
corresponding API's to access PRM module and
PRM register offsets & bit fields.

Signed-off-by: Rachna Patil <rachna@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/powerdomain.h           |    4 +-
 arch/arm/mach-omap2/powerdomain33xx.c       |  155 ++++++++++++
 arch/arm/mach-omap2/powerdomains33xx_data.c |  115 +++++++++
 arch/arm/mach-omap2/prm-regbits-33xx.h      |  357 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm33xx.h               |  123 +++++++++
 arch/arm/mach-omap2/prminst33xx.c           |   74 ++++++
 arch/arm/mach-omap2/prminst33xx.h           |   25 ++
 7 files changed, 852 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.h
 create mode 100644 arch/arm/mach-omap2/prminst33xx.c
 create mode 100644 arch/arm/mach-omap2/prminst33xx.h

diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a..9efa823 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -69,7 +69,7 @@
  * Maximum number of clockdomains that can be associated with a powerdomain.
  * CORE powerdomain on OMAP4 is the worst case
  */
-#define PWRDM_MAX_CLKDMS	9
+#define PWRDM_MAX_CLKDMS	11

 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -223,10 +223,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);

 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;

 /* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 0000000..80bfd42
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,155 @@
+/*
+ * AM33XX Powerdomain control
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+#include "prminst33xx.h"
+
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	am33xx_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+					(pwrst << OMAP_POWERSTATE_SHIFT),
+					pwrdm->prcm_offs, AM33XX_PM_PWSTCTRL);
+	return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTCTRL);
+	v &= OMAP_POWERSTATE_MASK;
+	v >>= OMAP_POWERSTATE_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTST);
+	v &= OMAP_POWERSTATEST_MASK;
+	v >>= OMAP_POWERSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTST);
+	v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+	v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+	am33xx_prminst_rmw_inst_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+			(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+			pwrdm->prcm_offs, AM33XX_PM_PWSTCTRL);
+	return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+	am33xx_prminst_rmw_inst_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+			AM33XX_LASTPOWERSTATEENTERED_MASK,
+			pwrdm->prcm_offs, AM33XX_PM_PWSTST);
+	return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	u32 v;
+
+	v = pwrst << __ffs(AM33XX_LOGICRETSTATE_MASK);
+	am33xx_prminst_rmw_inst_reg_bits(AM33XX_LOGICRETSTATE_MASK, v,
+			pwrdm->prcm_offs, AM33XX_PM_PWSTCTRL);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTST);
+	v &= AM33XX_LOGICSTATEST_MASK;
+	v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTCTRL);
+	v &= AM33XX_LOGICRETSTATE_MASK;
+	v >>= AM33XX_LOGICRETSTATE_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+	u32 c = 0;
+
+	/*
+	 * REVISIT: pwrdm_wait_transition() may be better implemented
+	 * via a callback and a periodic timer check -- how long do we expect
+	 * powerdomain transitions to take?
+	 */
+
+	/* XXX Is this udelay() value meaningful? */
+	while ((am33xx_prminst_read_inst_reg(pwrdm->prcm_offs, AM33XX_PM_PWSTST)
+		& OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT))
+		udelay(1);
+
+	if (c > PWRDM_TRANSITION_BAILOUT) {
+		printk(KERN_ERR "powerdomain: waited too long for "
+			"powerdomain %s to complete transition\n", pwrdm->name);
+		return -EAGAIN;
+	}
+
+	pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+	return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+	.pwrdm_set_next_pwrst		= am33xx_pwrdm_set_next_pwrst,
+	.pwrdm_read_next_pwrst		= am33xx_pwrdm_read_next_pwrst,
+	.pwrdm_read_pwrst		= am33xx_pwrdm_read_pwrst,
+	.pwrdm_read_prev_pwrst		= am33xx_pwrdm_read_prev_pwrst,
+	.pwrdm_set_logic_retst		= am33xx_pwrdm_set_logic_retst,
+	.pwrdm_read_logic_pwrst		= am33xx_pwrdm_read_logic_pwrst,
+	.pwrdm_read_logic_retst		= am33xx_pwrdm_read_logic_retst,
+	.pwrdm_clear_all_prev_pwrst	= am33xx_pwrdm_clear_all_prev_pwrst,
+	.pwrdm_set_lowpwrstchange	= am33xx_pwrdm_set_lowpwrstchange,
+	.pwrdm_wait_transition		= am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 0000000..e69e62a
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,115 @@
+/*
+ * AM33Xx Power domains framework
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prm33xx.h"
+
+static struct powerdomain gfx_33xx_pwrdm = {
+	.name			= "gfx_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_GFX_MOD,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 1,
+	.pwrsts_mem_ret		= {
+		[0] 	= PWRSTS_OFF_RET,		/* gfx_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]	= PWRSTS_ON,		/* gfx_mem */
+	},
+};
+
+static struct powerdomain rtc_33xx_pwrdm = {
+	.name			= "rtc_pwrdm",
+	.voltdm			= { .name = "rtc" },
+	.prcm_offs		= AM33XX_PRM_RTC_MOD,
+	.pwrsts			= PWRSTS_ON,
+};
+
+static struct powerdomain wkup_33xx_pwrdm = {
+	.name			= "wkup_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
+	.pwrsts			= PWRSTS_ON,
+};
+
+static struct powerdomain per_33xx_pwrdm = {
+	.name			= "per_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_PER_MOD,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.pwrsts_mem_ret		= {
+		[0]	= PWRSTS_OFF_RET,	/* icss_mem */
+		[1]	= PWRSTS_OFF_RET,	/* per_mem */
+		[2]	= PWRSTS_OFF_RET,	/* ram_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]	= PWRSTS_ON,		/* icss_mem */
+		[1]	= PWRSTS_ON,		/* per_mem */
+		[2]	= PWRSTS_ON,		/* ram_mem */
+	},
+};
+
+static struct powerdomain mpu_33xx_pwrdm = {
+	.name			= "mpu_pwrdm",
+	.voltdm			= { .name = "mpu" },
+	.prcm_offs		= AM33XX_PRM_MPU_MOD,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.pwrsts_mem_ret		= {
+		[0]	= PWRSTS_OFF_RET,	/* mpu_l1 */
+		[1]	= PWRSTS_OFF_RET,	/* mpu_l2 */
+		[2]	= PWRSTS_OFF_RET,	/* mpu_ram */
+	},
+	.pwrsts_mem_on		= {
+		[0]	= PWRSTS_ON,		/* mpu_l1 */
+		[1]	= PWRSTS_ON,		/* mpu_l2 */
+		[2]	= PWRSTS_ON,		/* mpu_ram */
+	},
+};
+
+static struct powerdomain cefuse_33xx_pwrdm = {
+	.name		= "cefuse_pwrdm",
+	.voltdm		= { .name = "core" },
+	.prcm_offs	= AM33XX_PRM_CEFUSE_MOD,
+	.pwrsts		= PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_am33xx[] __initdata = {
+	&gfx_33xx_pwrdm,
+	&rtc_33xx_pwrdm,
+	&wkup_33xx_pwrdm,
+	&per_33xx_pwrdm,
+	&mpu_33xx_pwrdm,
+	&cefuse_33xx_pwrdm,
+	NULL,
+};
+
+void __init am33xx_powerdomains_init(void)
+{
+	pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
+	pwrdm_register_pwrdms(powerdomains_am33xx);
+	pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 0000000..5299287
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
+/*
+ * AM33XX Power Management register bits
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+
+#include "prm.h"
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
+#define AM33XX_ABBOFF_ACT_EXPORT_MASK			BITFIELD(1, 1)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			BITFIELD(2, 2)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_AIPOFF_SHIFT				8
+#define AM33XX_AIPOFF_MASK				BITFIELD(8, 8)
+
+/* Used by PM_WKUP_PWRSTST */
+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
+#define AM33XX_DEBUGSS_MEM_STATEST_MASK			BITFIELD(17, 18)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
+#define AM33XX_DISABLE_RTA_EXPORT_MASK			BITFIELD(0, 0)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_EN_MASK			BITFIELD(12, 12)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_ST_MASK			BITFIELD(12, 12)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_EN_MASK			BITFIELD(14, 14)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_ST_MASK			BITFIELD(14, 14)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
+#define AM33XX_DPLL_DISP_RECAL_EN_MASK			BITFIELD(15, 15)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
+#define AM33XX_DPLL_DISP_RECAL_ST_MASK			BITFIELD(13, 13)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_EN_MASK			BITFIELD(11, 11)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_ST_MASK			BITFIELD(11, 11)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
+#define AM33XX_DPLL_PER_RECAL_EN_MASK			BITFIELD(13, 13)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
+#define AM33XX_DPLL_PER_RECAL_ST_MASK			BITFIELD(15, 15)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_EMULATION_M3_RST_SHIFT			6
+#define AM33XX_EMULATION_M3_RST_MASK			BITFIELD(6, 6)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_EMULATION_MPU_RST_SHIFT			5
+#define AM33XX_EMULATION_MPU_RST_MASK			BITFIELD(5, 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC1_EXPORT_SHIFT			3
+#define AM33XX_ENFUNC1_EXPORT_MASK			BITFIELD(3, 3)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC3_EXPORT_SHIFT			5
+#define AM33XX_ENFUNC3_EXPORT_MASK			BITFIELD(5, 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC4_SHIFT				6
+#define AM33XX_ENFUNC4_MASK				BITFIELD(6, 6)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC5_SHIFT				7
+#define AM33XX_ENFUNC5_MASK				BITFIELD(7, 7)
+
+/* Used by PRM_RSTST */
+#define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
+#define AM33XX_EXTERNAL_WARM_RST_MASK			BITFIELD(5, 5)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_FORCEWKUP_EN_SHIFT			10
+#define AM33XX_FORCEWKUP_EN_MASK			BITFIELD(10, 10)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_FORCEWKUP_ST_SHIFT			10
+#define AM33XX_FORCEWKUP_ST_MASK			BITFIELD(10, 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
+#define AM33XX_GFX_MEM_ONSTATE_MASK			BITFIELD(17, 18)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
+#define AM33XX_GFX_MEM_RETSTATE_MASK			BITFIELD(6, 6)
+
+/* Used by PM_GFX_PWRSTST */
+#define AM33XX_GFX_MEM_STATEST_SHIFT			4
+#define AM33XX_GFX_MEM_STATEST_MASK			BITFIELD(4, 5)
+
+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+#define AM33XX_GFX_RST_SHIFT				0
+#define AM33XX_GFX_RST_MASK				(1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_COLD_RST_SHIFT			0
+#define AM33XX_GLOBAL_COLD_RST_MASK			BITFIELD(0, 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
+#define AM33XX_GLOBAL_WARM_SW_RST_MASK			BITFIELD(1, 1)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
+#define AM33XX_ICECRUSHER_M3_RST_MASK			BITFIELD(7, 7)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
+#define AM33XX_ICECRUSHER_MPU_RST_MASK			BITFIELD(6, 6)
+
+/* Used by PRM_RSTST */
+#define AM33XX_ICEPICK_RST_SHIFT			9
+#define AM33XX_ICEPICK_RST_MASK				BITFIELD(9, 9)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_ICSS_LRST_SHIFT				1
+#define AM33XX_ICSS_LRST_MASK				BITFIELD(1, 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_ICSS_MEM_ONSTATE_SHIFT			5
+#define AM33XX_ICSS_MEM_ONSTATE_MASK			BITFIELD(5, 6)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_ICSS_MEM_RETSTATE_SHIFT			7
+#define AM33XX_ICSS_MEM_RETSTATE_MASK			BITFIELD(7, 7)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_ICSS_MEM_STATEST_SHIFT			23
+#define AM33XX_ICSS_MEM_STATEST_MASK			BITFIELD(23, 24)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_INTRANSITION_SHIFT			20
+#define AM33XX_INTRANSITION_MASK			BITFIELD(20, 20)
+
+/* Used by PM_CEFUSE_PWRSTST */
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
+
+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_SHIFT			2
+#define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
+
+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
+#define AM33XX_LOGICRETSTATE_3_3_MASK			BITFIELD(3, 3)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_LOGICSTATEST_SHIFT			2
+#define AM33XX_LOGICSTATEST_MASK			(1 << 2)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ */
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_ONSTATE_SHIFT			18
+#define AM33XX_MPU_L1_ONSTATE_MASK			BITFIELD(18, 19)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_RETSTATE_SHIFT			22
+#define AM33XX_MPU_L1_RETSTATE_MASK			BITFIELD(22, 22)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L1_STATEST_SHIFT			6
+#define AM33XX_MPU_L1_STATEST_MASK			BITFIELD(6, 7)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_ONSTATE_SHIFT			20
+#define AM33XX_MPU_L2_ONSTATE_MASK			BITFIELD(20, 21)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_RETSTATE_SHIFT			23
+#define AM33XX_MPU_L2_RETSTATE_MASK			BITFIELD(23, 23)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L2_STATEST_SHIFT			8
+#define AM33XX_MPU_L2_STATEST_MASK			BITFIELD(8, 9)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
+#define AM33XX_MPU_RAM_ONSTATE_MASK			BITFIELD(16, 17)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
+#define AM33XX_MPU_RAM_RETSTATE_MASK			BITFIELD(24, 24)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_RAM_STATEST_SHIFT			4
+#define AM33XX_MPU_RAM_STATEST_MASK			BITFIELD(4, 5)
+
+/* Used by PRM_RSTST */
+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK		BITFIELD(2, 2)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_PCHARGECNT_VALUE_SHIFT			0
+#define AM33XX_PCHARGECNT_VALUE_MASK			BITFIELD(0, 5)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PCI_LRST_SHIFT				0
+#define AM33XX_PCI_LRST_MASK				BITFIELD(0, 0)
+
+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
+#define AM33XX_PCI_LRST_5_5_SHIFT			5
+#define AM33XX_PCI_LRST_5_5_MASK			BITFIELD(5, 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_ONSTATE_SHIFT			25
+#define AM33XX_PER_MEM_ONSTATE_MASK			BITFIELD(25, 26)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_RETSTATE_SHIFT			29
+#define AM33XX_PER_MEM_RETSTATE_MASK			BITFIELD(29, 29)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PER_MEM_STATEST_SHIFT			17
+#define AM33XX_PER_MEM_STATEST_MASK			BITFIELD(17, 18)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define AM33XX_POWERSTATE_SHIFT				0
+#define AM33XX_POWERSTATE_MASK				BITFIELD(0, 1)
+
+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+#define AM33XX_POWERSTATEST_SHIFT			0
+#define AM33XX_POWERSTATEST_MASK			BITFIELD(0, 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
+#define AM33XX_RAM_MEM_ONSTATE_MASK			BITFIELD(30, 31)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
+#define AM33XX_RAM_MEM_RETSTATE_MASK			BITFIELD(27, 27)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_RAM_MEM_STATEST_SHIFT			21
+#define AM33XX_RAM_MEM_STATEST_MASK			BITFIELD(21, 22)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_RETMODE_ENABLE_SHIFT			0
+#define AM33XX_RETMODE_ENABLE_MASK			BITFIELD(0, 0)
+
+/* Used by REVISION_PRM */
+#define AM33XX_REV_SHIFT				0
+#define AM33XX_REV_MASK					BITFIELD(0, 7)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME1_SHIFT				0
+#define AM33XX_RSTTIME1_MASK				BITFIELD(0, 7)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME2_SHIFT				8
+#define AM33XX_RSTTIME2_MASK				BITFIELD(8, 12)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
+#define AM33XX_RST_GLOBAL_COLD_SW_MASK			BITFIELD(1, 1)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK			BITFIELD(0, 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_SLPCNT_VALUE_SHIFT			16
+#define AM33XX_SLPCNT_VALUE_MASK			BITFIELD(16, 23)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAMLDO_STATUS_SHIFT			8
+#define AM33XX_SRAMLDO_STATUS_MASK			BITFIELD(8, 8)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
+#define AM33XX_SRAM_IN_TRANSITION_MASK			BITFIELD(9, 9)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_STARTUP_COUNT_SHIFT			24
+#define AM33XX_STARTUP_COUNT_MASK			BITFIELD(24, 31)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_TRANSITION_EN_SHIFT			8
+#define AM33XX_TRANSITION_EN_MASK			BITFIELD(8, 8)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_TRANSITION_ST_SHIFT			8
+#define AM33XX_TRANSITION_ST_MASK			BITFIELD(8, 8)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_VSETUPCNT_VALUE_SHIFT			8
+#define AM33XX_VSETUPCNT_VALUE_MASK			BITFIELD(8, 15)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT0_RST_SHIFT				3
+#define AM33XX_WDT0_RST_MASK				BITFIELD(3, 3)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT1_RST_SHIFT				4
+#define AM33XX_WDT1_RST_MASK				BITFIELD(4, 4)
+
+/* Used by RM_WKUP_RSTCTRL */
+#define AM33XX_WKUP_M3_LRST_SHIFT			3
+#define AM33XX_WKUP_M3_LRST_MASK			BITFIELD(3, 3)
+
+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
+#define AM33XX_WKUP_M3_LRST_5_5_MASK			BITFIELD(5, 5)
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 0000000..0fd5c6e
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,123 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define AM33XX_PRM_BASE               0x44E00000
+
+#define AM33XX_PRM_REGADDR(inst, reg)                         \
+	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
+#define AM33XX_PRM_PER_MOD		0x0C00
+#define AM33XX_PRM_WKUP_MOD		0x0D00
+#define AM33XX_PRM_MPU_MOD		0x0E00
+#define AM33XX_PRM_DEVICE_MOD		0x0F00
+#define AM33XX_PRM_RTC_MOD		0x1000
+#define AM33XX_PRM_GFX_MOD		0x1100
+#define AM33XX_PRM_CEFUSE_MOD		0x1200
+
+/* Register offsets (used from OMAP4) */
+#define AM33XX_PM_PWSTCTRL		0x0000
+#define AM33XX_PM_PWSTST		0x0004
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define AM33XX_REVISION_PRM_OFFSET		0x0000
+#define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
+#define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
+#define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
+#define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+#define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
+#define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+
+/* PRM.PER_PRM register offsets */
+#define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+#define AM33XX_RM_PER_RSTST_OFFSET		0x0004
+#define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+#define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
+#define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+
+/* PRM.WKUP_PRM register offsets */
+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
+#define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+#define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+#define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
+#define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+
+/* PRM.MPU_PRM register offsets */
+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+#define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+#define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
+#define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+
+/* PRM.DEVICE_PRM register offsets */
+#define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
+#define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+#define AM33XX_PRM_RSTTIME_OFFSET		0x0004
+#define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+#define AM33XX_PRM_RSTST_OFFSET			0x0008
+#define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+#define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
+#define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+
+/* PRM.RTC_PRM register offsets */
+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+#define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+
+/* PRM.GFX_PRM register offsets */
+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+#define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
+#define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+#define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
+#define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+#define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
+#define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
+#define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+#endif
diff --git a/arch/arm/mach-omap2/prminst33xx.c b/arch/arm/mach-omap2/prminst33xx.c
new file mode 100644
index 0000000..88382ba
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst33xx.c
@@ -0,0 +1,74 @@
+/*
+ * AM33XX PRM instance functions
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "prm33xx.h"
+#include "prminst33xx.h"
+#include "prm-regbits-33xx.h"
+
+#define AM33XX_PRM_MOD_SIZE	0x100
+#define AM33XX_PRM_MOD_START	AM33XX_PRM_PER_MOD
+#define PRM_REG_SZ		0x4
+
+/*
+ * PRM Offsets are screwed up, and they are not consistent across modules.
+ * Below are the offsets for PWRSTCTRL and PWRSTST for respective modules.
+ */
+static u16 off_fixup[][2] = {
+	{ 0xC, 0x8 },	/* AM33XX_PRM_PER_MOD */
+	{ 0x4, 0x8 },	/* AM33XX_PRM_WKUP_MOD */
+	{ 0x0, 0x4 },	/* AM33XX_PRM_MPU_MOD */
+	/* XXX: PRM_DEVICE: offsets are invalid for powerdomain*/
+	{ 0x0, 0x0 },	/* AM33XX_PRM_DEVICE_MOD */
+	{ 0x0, 0x4 },	/* AM33XX_PRM_RTC_MOD */
+	{ 0x0, 0x10 },	/* AM33XX_PRM_GFX_MOD */
+	{ 0x0, 0x4 },	/* AM33XX_PRM_CEFUSE_MOD */
+};
+
+/* Read a register in a PRM instance */
+u32 am33xx_prminst_read_inst_reg(s16 inst, u16 idx)
+{
+	int i = (inst - AM33XX_PRM_MOD_START) / AM33XX_PRM_MOD_SIZE;
+
+	return __raw_readl(prm_base + inst + off_fixup[i][idx / PRM_REG_SZ]);
+}
+
+/* Write into a register in a PRM instance */
+void am33xx_prminst_write_inst_reg(u32 val, s16 inst, u16 idx)
+{
+	int i = (inst - AM33XX_PRM_MOD_START) / AM33XX_PRM_MOD_SIZE;
+
+	__raw_writel(val, prm_base + inst + off_fixup[i][idx / PRM_REG_SZ]);
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 am33xx_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+	u32 v;
+
+	v = am33xx_prminst_read_inst_reg(inst, idx);
+	v &= ~mask;
+	v |= bits;
+	am33xx_prminst_write_inst_reg(v, inst, idx);
+
+	return v;
+}
diff --git a/arch/arm/mach-omap2/prminst33xx.h b/arch/arm/mach-omap2/prminst33xx.h
new file mode 100644
index 0000000..0f167c0
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst33xx.h
@@ -0,0 +1,25 @@
+/*
+ * AM33XX Power/Reset Management (PRM) function prototypes
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
+#define __ARCH_ASM_MACH_OMAP2_PRMINST33XX_H
+
+extern u32 am33xx_prminst_read_inst_reg(s16 inst, u16 idx);
+extern void am33xx_prminst_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_prminst_rmw_inst_reg_bits(u32 mask, u32 bits,
+					   s16 inst, s16 idx);
+extern void am33xx_prm_global_warm_sw_reset(void);
+
+#endif
--
1.7.0.4

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> From: Afzal Mohammed <afzal@ti.com>
>
> This patch adds AM33XX power domain data,
> corresponding API's to access PRM module and
> PRM register offsets & bit fields.
>
> Signed-off-by: Rachna Patil <rachna@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>

First some general comments:

At first glance, it seems like there could be much more reuse with OMAP4
code here.  From what I see, AM33x has only one partition compared to
several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
functions and just use a single partition.

IOW, it seems to me that all the pwrdm_ops could be shared with OMAP4.

>From what I read (after an admittedly quick glance), the main thing you
need is a way to override the PRM offsets due to the fact that some
crazy person decided to make each instance different.

If you modified the OMAP4 base so that the _prminst_read_inst_reg()
could be customized, wouldn't that work for AM33xx?

> ---
>  arch/arm/mach-omap2/powerdomain.h           |    4 +-
>  arch/arm/mach-omap2/powerdomain33xx.c       |  155 ++++++++++++
>  arch/arm/mach-omap2/powerdomains33xx_data.c |  115 +++++++++
>  arch/arm/mach-omap2/prm-regbits-33xx.h      |  357 +++++++++++++++++++++++++++
>  arch/arm/mach-omap2/prm33xx.h               |  123 +++++++++
>  arch/arm/mach-omap2/prminst33xx.c           |   74 ++++++
>  arch/arm/mach-omap2/prminst33xx.h           |   25 ++
>  7 files changed, 852 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
>  create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
>  create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
>  create mode 100644 arch/arm/mach-omap2/prm33xx.h
>  create mode 100644 arch/arm/mach-omap2/prminst33xx.c
>  create mode 100644 arch/arm/mach-omap2/prminst33xx.h
>
> diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
> index 0d72a8a..9efa823 100644
> --- a/arch/arm/mach-omap2/powerdomain.h
> +++ b/arch/arm/mach-omap2/powerdomain.h
> @@ -69,7 +69,7 @@
>   * Maximum number of clockdomains that can be associated with a powerdomain.
>   * CORE powerdomain on OMAP4 is the worst case
>   */
> -#define PWRDM_MAX_CLKDMS	9
> +#define PWRDM_MAX_CLKDMS	11

Comment before this needs update  as well.

>  /* XXX A completely arbitrary number. What is reasonable here? */
>  #define PWRDM_TRANSITION_BAILOUT 100000
> @@ -223,10 +223,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
>  extern void omap242x_powerdomains_init(void);
>  extern void omap243x_powerdomains_init(void);
>  extern void omap3xxx_powerdomains_init(void);
> +extern void am33xx_powerdomains_init(void);
>  extern void omap44xx_powerdomains_init(void);
>
>  extern struct pwrdm_ops omap2_pwrdm_operations;
>  extern struct pwrdm_ops omap3_pwrdm_operations;
> +extern struct pwrdm_ops am33xx_pwrdm_operations;
>  extern struct pwrdm_ops omap4_pwrdm_operations;
>
>  /* Common Internal functions used across OMAP rev's */

[...]

> diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
> new file mode 100644
> index 0000000..0fd5c6e
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prm33xx.h
> @@ -0,0 +1,123 @@
> +/*
> + * AM33XX PRM instance offset macros
> + *
> + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
> +#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
> +
> +#include "prcm-common.h"
> +#include "prm.h"
> +
> +#define AM33XX_PRM_BASE               0x44E00000
> +
> +#define AM33XX_PRM_REGADDR(inst, reg)                         \
> +	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
> +
> +
> +/* PRM instances */
> +#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
> +#define AM33XX_PRM_PER_MOD		0x0C00
> +#define AM33XX_PRM_WKUP_MOD		0x0D00
> +#define AM33XX_PRM_MPU_MOD		0x0E00
> +#define AM33XX_PRM_DEVICE_MOD		0x0F00
> +#define AM33XX_PRM_RTC_MOD		0x1000
> +#define AM33XX_PRM_GFX_MOD		0x1100
> +#define AM33XX_PRM_CEFUSE_MOD		0x1200
> +
> +/* Register offsets (used from OMAP4) */

Probably could just include prm44xx.h and use OMAP4_PM_... instead.

> +#define AM33XX_PM_PWSTCTRL		0x0000
> +#define AM33XX_PM_PWSTST		0x0004

However, since thes are just dummy offsets into a "fixup" table anyways,
maybe it's best to use use 0 and 1 here and have a comment here to that
effect.   Otherwise, it's a bit confusing since one would assume these
are actual register offsets.

[...]

> diff --git a/arch/arm/mach-omap2/prminst33xx.c b/arch/arm/mach-omap2/prminst33xx.c
> new file mode 100644
> index 0000000..88382ba
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prminst33xx.c
> @@ -0,0 +1,74 @@
> +/*
> + * AM33XX PRM instance functions
> + *
> + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +
> +#include <plat/common.h>
> +
> +#include "prm33xx.h"
> +#include "prminst33xx.h"
> +#include "prm-regbits-33xx.h"
> +
> +#define AM33XX_PRM_MOD_SIZE	0x100
> +#define AM33XX_PRM_MOD_START	AM33XX_PRM_PER_MOD
> +#define PRM_REG_SZ		0x4
> +
> +/*
> + * PRM Offsets are screwed up, and they are not consistent across modules.
> + * Below are the offsets for PWRSTCTRL and PWRSTST for respective modules.
> + */
> +static u16 off_fixup[][2] = {
> +	{ 0xC, 0x8 },	/* AM33XX_PRM_PER_MOD */
> +	{ 0x4, 0x8 },	/* AM33XX_PRM_WKUP_MOD */
> +	{ 0x0, 0x4 },	/* AM33XX_PRM_MPU_MOD */
> +	/* XXX: PRM_DEVICE: offsets are invalid for powerdomain*/
> +	{ 0x0, 0x0 },	/* AM33XX_PRM_DEVICE_MOD */
> +	{ 0x0, 0x4 },	/* AM33XX_PRM_RTC_MOD */
> +	{ 0x0, 0x10 },	/* AM33XX_PRM_GFX_MOD */
> +	{ 0x0, 0x4 },	/* AM33XX_PRM_CEFUSE_MOD */
> +};

Please use the #define values from prm-regbits...h

[...]

Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 6:34 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal; Patil,
> Rachna
> Subject: Re: [RFC PATCH 03/11] arm:omap:am33xx: Add power domain data
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > From: Afzal Mohammed <afzal@ti.com>
> >
> > This patch adds AM33XX power domain data,
> > corresponding API's to access PRM module and
> > PRM register offsets & bit fields.
> >
> > Signed-off-by: Rachna Patil <rachna@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> 
> First some general comments:
> 
> At first glance, it seems like there could be much more reuse with OMAP4
> code here.  From what I see, AM33x has only one partition compared to
> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
> functions and just use a single partition.
Kevin,

Indeed it looks close to OMAP4, but it becomes difficult and ugly once you
Start getting into implementation details, for example,

 - All PRM offsets don't match, you will end up with
cpu_is_xxx check and handle this. Applicable to all power domains.

	OMAP4430_PRM_MPU_INST           0x0300
	Vs
	AM33XX_PRM_MPU_MOD              0x0E00

	OMAP4430_PRM_WKUP_INST          0x1700
	Vs
	AM33XX_PRM_WKUP_MOD             0x0D00

 - Also there are some differences in logic states of domains as well.

Another important point is, we have considered AM33xx as OMAP3
family of device (ARCH_OMAP3).
So you may end up with number of cpu_is_xxx checks in code.

> 
> IOW, it seems to me that all the pwrdm_ops could be shared with OMAP4.
>
> From what I read (after an admittedly quick glance), the main thing you
> need is a way to override the PRM offsets due to the fact that some
> crazy person decided to make each instance different.
> 
This was one of the major reason why I had chosen and implemented separately
for AM33xx. 


> If you modified the OMAP4 base so that the _prminst_read_inst_reg()
> could be customized, wouldn't that work for AM33xx?
> 
> > ---
> >  arch/arm/mach-omap2/powerdomain.h           |    4 +-
> >  arch/arm/mach-omap2/powerdomain33xx.c       |  155 ++++++++++++
> >  arch/arm/mach-omap2/powerdomains33xx_data.c |  115 +++++++++
> >  arch/arm/mach-omap2/prm-regbits-33xx.h      |  357
> +++++++++++++++++++++++++++
> >  arch/arm/mach-omap2/prm33xx.h               |  123 +++++++++
> >  arch/arm/mach-omap2/prminst33xx.c           |   74 ++++++
> >  arch/arm/mach-omap2/prminst33xx.h           |   25 ++
> >  7 files changed, 852 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
> >  create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
> >  create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
> >  create mode 100644 arch/arm/mach-omap2/prm33xx.h
> >  create mode 100644 arch/arm/mach-omap2/prminst33xx.c
> >  create mode 100644 arch/arm/mach-omap2/prminst33xx.h
> >
> > diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-
> omap2/powerdomain.h
> > index 0d72a8a..9efa823 100644
> > --- a/arch/arm/mach-omap2/powerdomain.h
> > +++ b/arch/arm/mach-omap2/powerdomain.h
> > @@ -69,7 +69,7 @@
> >   * Maximum number of clockdomains that can be associated with a
> powerdomain.
> >   * CORE powerdomain on OMAP4 is the worst case
> >   */
> > -#define PWRDM_MAX_CLKDMS	9
> > +#define PWRDM_MAX_CLKDMS	11
> 
> Comment before this needs update  as well.
> 
Ok.

> >  /* XXX A completely arbitrary number. What is reasonable here? */
> >  #define PWRDM_TRANSITION_BAILOUT 100000
> > @@ -223,10 +223,12 @@ bool pwrdm_can_ever_lose_context(struct
> powerdomain *pwrdm);
> >  extern void omap242x_powerdomains_init(void);
> >  extern void omap243x_powerdomains_init(void);
> >  extern void omap3xxx_powerdomains_init(void);
> > +extern void am33xx_powerdomains_init(void);
> >  extern void omap44xx_powerdomains_init(void);
> >
> >  extern struct pwrdm_ops omap2_pwrdm_operations;
> >  extern struct pwrdm_ops omap3_pwrdm_operations;
> > +extern struct pwrdm_ops am33xx_pwrdm_operations;
> >  extern struct pwrdm_ops omap4_pwrdm_operations;
> >
> >  /* Common Internal functions used across OMAP rev's */
> 
> [...]
> 
> > diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-
> omap2/prm33xx.h
> > new file mode 100644
> > index 0000000..0fd5c6e
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/prm33xx.h
> > @@ -0,0 +1,123 @@
> > +/*
> > + * AM33XX PRM instance offset macros
> > + *
> > + * Copyright (C) 2011 Texas Instruments Incorporated -
> http://www.ti.com/
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
> > +#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
> > +
> > +#include "prcm-common.h"
> > +#include "prm.h"
> > +
> > +#define AM33XX_PRM_BASE               0x44E00000
> > +
> > +#define AM33XX_PRM_REGADDR(inst, reg)                         \
> > +	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
> > +
> > +
> > +/* PRM instances */
> > +#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
> > +#define AM33XX_PRM_PER_MOD		0x0C00
> > +#define AM33XX_PRM_WKUP_MOD		0x0D00
> > +#define AM33XX_PRM_MPU_MOD		0x0E00
> > +#define AM33XX_PRM_DEVICE_MOD		0x0F00
> > +#define AM33XX_PRM_RTC_MOD		0x1000
> > +#define AM33XX_PRM_GFX_MOD		0x1100
> > +#define AM33XX_PRM_CEFUSE_MOD		0x1200
> > +
> > +/* Register offsets (used from OMAP4) */
> 
> Probably could just include prm44xx.h and use OMAP4_PM_... instead.
> 
> > +#define AM33XX_PM_PWSTCTRL		0x0000
> > +#define AM33XX_PM_PWSTST		0x0004
> 
> However, since thes are just dummy offsets into a "fixup" table anyways,
> maybe it's best to use use 0 and 1 here and have a comment here to that
> effect.   Otherwise, it's a bit confusing since one would assume these
> are actual register offsets.
> 

As per the logic, used below in prminst API's, we need 0x0, 0x4, 0x8, 0xc
In order to parse the table and get exact offset for the register.

Due to that crazy person, whole offsets are really screwed up,
I could not able to get any logic/formula which results into
following offsets (mentioned in table).


> [...]
> 
> > diff --git a/arch/arm/mach-omap2/prminst33xx.c b/arch/arm/mach-
> omap2/prminst33xx.c
> > new file mode 100644
> > index 0000000..88382ba
> > --- /dev/null
> > +++ b/arch/arm/mach-omap2/prminst33xx.c
> > @@ -0,0 +1,74 @@
> > +/*
> > + * AM33XX PRM instance functions
> > + *
> > + * Copyright (C) 2011 Texas Instruments Incorporated -
> http://www.ti.com/
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/errno.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +
> > +#include <plat/common.h>
> > +
> > +#include "prm33xx.h"
> > +#include "prminst33xx.h"
> > +#include "prm-regbits-33xx.h"
> > +
> > +#define AM33XX_PRM_MOD_SIZE	0x100
> > +#define AM33XX_PRM_MOD_START	AM33XX_PRM_PER_MOD
> > +#define PRM_REG_SZ		0x4
> > +
> > +/*
> > + * PRM Offsets are screwed up, and they are not consistent across
> modules.
> > + * Below are the offsets for PWRSTCTRL and PWRSTST for respective
> modules.
> > + */
> > +static u16 off_fixup[][2] = {
> > +	{ 0xC, 0x8 },	/* AM33XX_PRM_PER_MOD */
> > +	{ 0x4, 0x8 },	/* AM33XX_PRM_WKUP_MOD */
> > +	{ 0x0, 0x4 },	/* AM33XX_PRM_MPU_MOD */
> > +	/* XXX: PRM_DEVICE: offsets are invalid for powerdomain*/
> > +	{ 0x0, 0x0 },	/* AM33XX_PRM_DEVICE_MOD */
> > +	{ 0x0, 0x4 },	/* AM33XX_PRM_RTC_MOD */
> > +	{ 0x0, 0x10 },	/* AM33XX_PRM_GFX_MOD */
> > +	{ 0x0, 0x4 },	/* AM33XX_PRM_CEFUSE_MOD */
> > +};
> 
> Please use the #define values from prm-regbits...h
> 

Ok.

Thanks,
Vaibhav

> [...]
> 
> Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Kevin Hilman]

"Hiremath, Vaibhav" <hvaibhav@ti.com> writes:

>> -----Original Message-----
>> From: Hilman, Kevin
>> Sent: Thursday, December 01, 2011 6:34 AM
>> To: Hiremath, Vaibhav
>> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
>> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal; Patil,
>> Rachna
>> Subject: Re: [RFC PATCH 03/11] arm:omap:am33xx: Add power domain data
>> 
>> Vaibhav Hiremath <hvaibhav@ti.com> writes:
>> 
>> > From: Afzal Mohammed <afzal@ti.com>
>> >
>> > This patch adds AM33XX power domain data,
>> > corresponding API's to access PRM module and
>> > PRM register offsets & bit fields.
>> >
>> > Signed-off-by: Rachna Patil <rachna@ti.com>
>> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
>> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
>> 
>> First some general comments:
>> 
>> At first glance, it seems like there could be much more reuse with OMAP4
>> code here.  From what I see, AM33x has only one partition compared to
>> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
>> functions and just use a single partition.
> Kevin,
>
> Indeed it looks close to OMAP4, but it becomes difficult and ugly once you
> Start getting into implementation details, for example,
>
>  - All PRM offsets don't match, you will end up with
> cpu_is_xxx check and handle this. Applicable to all power domains.
>
> 	OMAP4430_PRM_MPU_INST           0x0300
> 	Vs
> 	AM33XX_PRM_MPU_MOD              0x0E00
>
> 	OMAP4430_PRM_WKUP_INST          0x1700
> 	Vs
> 	AM33XX_PRM_WKUP_MOD             0x0D00
>
>  - Also there are some differences in logic states of domains as well.
>
> Another important point is, we have considered AM33xx as OMAP3 family
> of device (ARCH_OMAP3).  So you may end up with number of cpu_is_xxx
> checks in code.

If we end up with cpu_is_* checks in the code, we're doing it wrong.

I understand there are lots of differences with OMAP4, but from what I'm
looking at (at least for the power domains in this patch) there most of
those differences are handled in the data files, and the code could be
shared.

For example, looking at powerdomain33xx.c, this looks exactly like the
OMAP4 version except

- you have 2 new AM33XX_PRM_* defines (which are the same as OMAP4 version)
- you have a new register access functions: am33xx_prminst_read_inst_reg()...

So, my question is: if you could update the OMAP4 code to be able to
override the register access read/write functions, would you even need a
new powerdomain33xx.c?

Your am33xx_ version doesn't take a partition argument, but that would
be easy to remedy, and the AM33x powerdomains could be updated to all
declare a default partition.

Anyways, I'll let Benoit/Paul/Rajendra take it from here, as they're the
ones who know this code the best.

Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Rajendra Nayak]

[..]
>> First some general comments:
>>
>> At first glance, it seems like there could be much more reuse with OMAP4
>> code here.  From what I see, AM33x has only one partition compared to
>> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
>> functions and just use a single partition.
> Kevin,
>
> Indeed it looks close to OMAP4, but it becomes difficult and ugly once you
> Start getting into implementation details, for example,
>
>   - All PRM offsets don't match, you will end up with
> cpu_is_xxx check and handle this. Applicable to all power domains.
>
> 	OMAP4430_PRM_MPU_INST           0x0300
> 	Vs
> 	AM33XX_PRM_MPU_MOD              0x0E00
>
> 	OMAP4430_PRM_WKUP_INST          0x1700
> 	Vs
> 	AM33XX_PRM_WKUP_MOD             0x0D00

The above prcm offsets being different on am33xx doesn't really
seem to be the issue since its already part of the powerdomain
struct. See how omap2 and omap3 have different offsets and still end
up using common code. You won't need any cpu_is_* checks for those.

The real problem however seems to be with the completely different
PWSTCTRL and PWSTST offsets. They seem to be so messed up that they are
not even consistent across all powerdomains in the same SoC.
The only solution I could think of to handle these was if we had
a provision to specify the offsets on a per powerdomain level by
adding them to the powerdomain struct. It could be populated only
on SoC's which have these weirdly different offsets and for the rest
it could just get initialized with fixed values for all powerdomains
at init.

Kevin/Paul/Benoit any thoughts?

>
>   - Also there are some differences in logic states of domains as well.
>
> Another important point is, we have considered AM33xx as OMAP3
> family of device (ARCH_OMAP3).
> So you may end up with number of cpu_is_xxx checks in code.
>
>>
>> IOW, it seems to me that all the pwrdm_ops could be shared with OMAP4.
>>
>>  From what I read (after an admittedly quick glance), the main thing you
>> need is a way to override the PRM offsets due to the fact that some
>> crazy person decided to make each instance different.
>>
> This was one of the major reason why I had chosen and implemented separately
> for AM33xx.
>
>

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Kevin Hilman]

Rajendra Nayak <rnayak@ti.com> writes:

> [..]
>>> First some general comments:
>>>
>>> At first glance, it seems like there could be much more reuse with OMAP4
>>> code here.  From what I see, AM33x has only one partition compared to
>>> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
>>> functions and just use a single partition.
>> Kevin,
>>
>> Indeed it looks close to OMAP4, but it becomes difficult and ugly once you
>> Start getting into implementation details, for example,
>>
>>   - All PRM offsets don't match, you will end up with
>> cpu_is_xxx check and handle this. Applicable to all power domains.
>>
>> 	OMAP4430_PRM_MPU_INST           0x0300
>> 	Vs
>> 	AM33XX_PRM_MPU_MOD              0x0E00
>>
>> 	OMAP4430_PRM_WKUP_INST          0x1700
>> 	Vs
>> 	AM33XX_PRM_WKUP_MOD             0x0D00
>
> The above prcm offsets being different on am33xx doesn't really
> seem to be the issue since its already part of the powerdomain
> struct. See how omap2 and omap3 have different offsets and still end
> up using common code. You won't need any cpu_is_* checks for those.
>
> The real problem however seems to be with the completely different
> PWSTCTRL and PWSTST offsets. They seem to be so messed up that they are
> not even consistent across all powerdomains in the same SoC.
> The only solution I could think of to handle these was if we had
> a provision to specify the offsets on a per powerdomain level by
> adding them to the powerdomain struct. It could be populated only
> on SoC's which have these weirdly different offsets and for the rest
> it could just get initialized with fixed values for all powerdomains
> at init.
>
> Kevin/Paul/Benoit any thoughts?
>

Something tells me that AM33x is not the last device we're going to see
where there clearly wansn't a unified design around PRCM integration.

So I suspect adding this to the powerdomain struct is the best way to
go, but Paul/Benoit should make the final call.

Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Nori, Sekhar]

On Thu, Dec 01, 2011 at 06:34:19, Hilman, Kevin wrote:
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > From: Afzal Mohammed <afzal@ti.com>
> >
> > This patch adds AM33XX power domain data,
> > corresponding API's to access PRM module and
> > PRM register offsets & bit fields.
> >
> > Signed-off-by: Rachna Patil <rachna@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> 
> First some general comments:
> 
> At first glance, it seems like there could be much more reuse with OMAP4
> code here.  From what I see, AM33x has only one partition compared to
> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
> functions and just use a single partition.
> 
> IOW, it seems to me that all the pwrdm_ops could be shared with OMAP4.
> 
> From what I read (after an admittedly quick glance), the main thing you
> need is a way to override the PRM offsets due to the fact that some
> crazy person decided to make each instance different.

If its any consolation, this has been fed back to the
chip designers and is expected to be corrected for the
next AM335x derivative.

Thanks,
Sekhar

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Kevin Hilman]

"Nori, Sekhar" <nsekhar@ti.com> writes:

> On Thu, Dec 01, 2011 at 06:34:19, Hilman, Kevin wrote:
>> Vaibhav Hiremath <hvaibhav@ti.com> writes:
>> 
>> > From: Afzal Mohammed <afzal@ti.com>
>> >
>> > This patch adds AM33XX power domain data,
>> > corresponding API's to access PRM module and
>> > PRM register offsets & bit fields.
>> >
>> > Signed-off-by: Rachna Patil <rachna@ti.com>
>> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
>> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
>> 
>> First some general comments:
>> 
>> At first glance, it seems like there could be much more reuse with OMAP4
>> code here.  From what I see, AM33x has only one partition compared to
>> several on OMAP4, but that doesn't mean you couldn't reuse the OMAP4
>> functions and just use a single partition.
>> 
>> IOW, it seems to me that all the pwrdm_ops could be shared with OMAP4.
>> 
>> From what I read (after an admittedly quick glance), the main thing you
>> need is a way to override the PRM offsets due to the fact that some
>> crazy person decided to make each instance different.
>
> If its any consolation, this has been fed back to the chip designers
> and is expected to be corrected for the next AM335x derivative.

Great, Thanks!   

Assuming mainline kernel support is a priority for the other SoCs in
this family, keeping SW compatibility with other existing SoCs in the
OMAP family should be a high priority.  This is especially true when
large portions of the IP are reused from existing SoCs, as is clearly
the case in AM33x.

Kevin

[RFC PATCH 03/11] arm:omap:am33xx: Add power domain data

[Rajendra Nayak]

[..]
> diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
> new file mode 100644
> index 0000000..5299287
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
> @@ -0,0 +1,357 @@
> +/*
> + * AM33XX Power Management register bits
> + *
> + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
> +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
> +
> +#include "prm.h"
> +
> +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
> +#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
> +#define AM33XX_ABBOFF_ACT_EXPORT_MASK			BITFIELD(1, 1)

This seems like an output from an old autogen script. The BITFIELD macro
does not exist anymore.

[RFC PATCH 04/11] arm:omap:am33xx: Integrate powerdomain to OMAP power framework

[Vaibhav Hiremath]

From: Afzal Mohammed <afzal@ti.com>

Hook up AM33XX power domain to OMAP framework.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/Makefile |    3 +++
 arch/arm/mach-omap2/io.c     |    1 +
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4a9a61..b5f20d2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -81,6 +81,7 @@ endif
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 					   vc3xxx_data.o vp3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst33xx.o
 # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
 # will be removed once the OMAP4 part of the codebase is converted to
 # use OMAP4-specific PRCM functions.
@@ -110,6 +111,8 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(powerdomain-common) \
 					   powerdomain2xxx_3xxx.o \
 					   powerdomains3xxx_data.o \
 					   powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= powerdomain33xx.o \
+					   powerdomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 					   powerdomain44xx.o \
 					   powerdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b67d2ca..7ea23d8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -466,6 +466,7 @@ void __init am33xx_init_early(void)
 	omap2_set_globals_am33xx();
 	omap_common_init_early();
 	am33xx_voltagedomains_init();
+	am33xx_powerdomains_init();
 	omap3xxx_clk_init();
 }
 #endif
--
1.7.0.4

[RFC PATCH 04/11] arm:omap:am33xx: Integrate powerdomain to OMAP power framework

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> From: Afzal Mohammed <afzal@ti.com>
>
> Hook up AM33XX power domain to OMAP framework.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

Should be combined with previous patch.

Kevin

[RFC PATCH 04/11] arm:omap:am33xx: Integrate powerdomain to OMAP power framework

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 6:35 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal
> Subject: Re: [RFC PATCH 04/11] arm:omap:am33xx: Integrate powerdomain to
> OMAP power framework
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > From: Afzal Mohammed <afzal@ti.com>
> >
> > Hook up AM33XX power domain to OMAP framework.
> >
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Should be combined with previous patch.
> 

Ok, will take care in next version.

Thanks,
Vaibhav

> Kevin

[RFC PATCH 06/11] arm:omap:am33xx: Integrate clock & clockdomain to OMAP clock framework

[Vaibhav Hiremath]

From: Afzal Mohammed <afzal@ti.com>

Hook up AM33XX clock & clock domain data to OMAP framework.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/Makefile               |    4 +++-
 arch/arm/mach-omap2/clock3xxx_data.c       |    5 +++--
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c |   18 ++++++++++++++++--
 arch/arm/mach-omap2/io.c                   |    1 +
 4 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b5f20d2..19330dc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -81,7 +81,7 @@ endif
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 					   vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst33xx.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst33xx.o cm33xx.o
 # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
 # will be removed once the OMAP4 part of the codebase is converted to
 # use OMAP4-specific PRCM functions.
@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o \
 					   clockdomain2xxx_3xxx.o \
 					   clockdomains2xxx_3xxx_data.o \
 					   clockdomains3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= clockdomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o \
 					   clockdomain44xx.o \
 					   clockdomains44xx_data.o
@@ -145,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \
 					   clock3517.o clock36xx.o \
 					   dpll3xxx.o clock3xxx_data.o \
 					   clkt_iclk.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= clock33xx_data.o clock33xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
 					   dpll3xxx.o dpll44xx.o

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index c1ab6bc..9fe72da 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -27,6 +27,7 @@
 #include "clock34xx.h"
 #include "clock36xx.h"
 #include "clock3517.h"
+#include "clock33xx.h"

 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
@@ -3518,8 +3519,8 @@ int __init omap3xxx_clk_init(void)
 		cpu_mask = RATE_IN_TI816X;
 		cpu_clkflg = CK_TI816X;
 	} else if (cpu_is_am33xx()) {
-		cpu_mask = RATE_IN_AM33XX;
-		cpu_clkflg = CK_AM33XX;
+		am33xx_clk_init();
+		return 0;
 	} else if (cpu_is_omap34xx()) {
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			cpu_mask = RATE_IN_3430ES1;
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index a0d68db..edcab10 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -147,6 +147,9 @@ static void _enable_hwsup(struct clockdomain *clkdm)
 	if (cpu_is_omap24xx())
 		omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 					       clkdm->clktrctrl_mask);
+	else if (cpu_is_am33xx())
+		am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
+					       clkdm->clktrctrl_mask);
 	else if (cpu_is_omap34xx())
 		omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 					       clkdm->clktrctrl_mask);
@@ -157,6 +160,9 @@ static void _disable_hwsup(struct clockdomain *clkdm)
 	if (cpu_is_omap24xx())
 		omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 						clkdm->clktrctrl_mask);
+	else if (cpu_is_am33xx())
+		am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs,
+					       clkdm->clktrctrl_mask);
 	else if (cpu_is_omap34xx())
 		omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 						clkdm->clktrctrl_mask);
@@ -211,14 +217,22 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)

 static int omap3_clkdm_sleep(struct clockdomain *clkdm)
 {
-	omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+	if (cpu_is_am33xx())
+		am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs,
+				clkdm->clktrctrl_mask);
+	else
+		omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
 				clkdm->clktrctrl_mask);
 	return 0;
 }

 static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
 {
-	omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+	if (cpu_is_am33xx())
+		am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs,
+				clkdm->clktrctrl_mask);
+	else
+		omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
 				clkdm->clktrctrl_mask);
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 7ea23d8..82e2817 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -467,6 +467,7 @@ void __init am33xx_init_early(void)
 	omap_common_init_early();
 	am33xx_voltagedomains_init();
 	am33xx_powerdomains_init();
+	am33xx_clockdomains_init();
 	omap3xxx_clk_init();
 }
 #endif
--
1.7.0.4

[RFC PATCH 07/11] arm:omap:am33xx: Add irq, dma and module base addr to SoC header files

[Vaibhav Hiremath]

This patch creats seperate irq and dma defination header file
and updates the module base addresses required for HWMOD data.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/plat-omap/include/plat/am33xx.h    |   40 ++++++++
 arch/arm/plat-omap/include/plat/dma-33xx.h  |   85 ++++++++++++++++
 arch/arm/plat-omap/include/plat/dma.h       |    1 +
 arch/arm/plat-omap/include/plat/irqs-33xx.h |  143 +++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h      |    1 +
 arch/arm/plat-omap/include/plat/serial.h    |    5 +
 6 files changed, 275 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/dma-33xx.h
 create mode 100644 arch/arm/plat-omap/include/plat/irqs-33xx.h

diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
index 06c19bb..1162d82 100644
--- a/arch/arm/plat-omap/include/plat/am33xx.h
+++ b/arch/arm/plat-omap/include/plat/am33xx.h
@@ -22,4 +22,44 @@
 #define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE	0x44E00000

+#define AM33XX_GPIO0_BASE	0x44E07000
+#define AM33XX_GPIO1_BASE	0x4804C000
+#define AM33XX_GPIO2_BASE	0x481AC000
+#define AM33XX_GPIO3_BASE	0x481AE000
+
+#define AM33XX_TIMER0_BASE	0x44E05000
+#define AM33XX_TIMER1_BASE	0x44E31000
+#define AM33XX_TIMER2_BASE	0x48040000
+#define AM33XX_TIMER3_BASE	0x48042000
+#define AM33XX_TIMER4_BASE	0x48044000
+#define AM33XX_TIMER5_BASE	0x48046000
+#define AM33XX_TIMER6_BASE	0x48048000
+#define AM33XX_TIMER7_BASE	0x4804A000
+
+#define AM33XX_WDT1_BASE	0x44E35000
+
+#define AM33XX_TSC_BASE		0x44E0D000
+#define AM33XX_RTC_BASE		0x44E3E000
+
+#define AM33XX_ASP0_BASE	0x48038000
+#define AM33XX_ASP1_BASE	0x4803C000
+
+#define AM33XX_MMC0_BASE	0x48060100
+#define AM33XX_MMC1_BASE	0x481D8100
+#define AM33XX_MMC2_BASE	0x47810100
+
+#define AM33XX_I2C0_BASE	0x44E0B000
+#define AM33XX_I2C1_BASE	0x4802A000
+#define AM33XX_I2C2_BASE	0x4819C000
+
+#define AM33XX_SPI0_BASE	0x48030000
+#define AM33XX_SPI1_BASE	0x481A0000
+
+#define AM33XX_DCAN0_BASE	0x481CC000
+#define AM33XX_DCAN1_BASE	0x481D0000
+
+#define AM33XX_USBSS_BASE	0x47400000
+#define AM33XX_USB0_BASE	0x47401000
+#define AM33XX_USB1_BASE	0x47401800
+
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/dma-33xx.h b/arch/arm/plat-omap/include/plat/dma-33xx.h
new file mode 100644
index 0000000..f78edb4
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dma-33xx.h
@@ -0,0 +1,85 @@
+/*
+ * AM33XX SDMA channel definitions
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
+#define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
+
+
+#define AM33XX_DMA_ICSS0_7				0
+#define AM33XX_DMA_ICSS0_6				1
+#define AM33XX_DMA_MMCHS1_W				2
+#define AM33XX_DMA_MMCHS1_R				3
+#define AM33XX_DMA_AESEIP36T0_CTXIN			4
+#define AM33XX_DMA_AESEIP36T0_DIN			5
+#define AM33XX_DMA_AESEIP36T0_DOUT			6
+#define AM33XX_DMA_AESEIP36T0_CTXOUT			7
+#define AM33XX_DMA_MCASP0_X				8
+#define AM33XX_DMA_MCASP0_R				9
+#define AM33XX_DMA_MCASP1_X				10
+#define AM33XX_DMA_MCASP1_R				11
+#define AM33XX_DMA_MCASP2_X				12
+#define AM33XX_DMA_MCASP2_R				13
+#define AM33XX_DMA_PWMSS0_EPWM				14
+#define AM33XX_DMA_PWMSS1_EPWM				15
+#define AM33XX_DMA_SPIOCP0_CH0W				16
+#define AM33XX_DMA_SPIOCP0_CH0R				17
+#define AM33XX_DMA_SPIOCP0_CH1W				18
+#define AM33XX_DMA_SPIOCP0_CH1R				19
+#define AM33XX_DMA_SPIOCP3_CH1W				20
+#define AM33XX_DMA_SPIOCP3_CH1R				21
+#define AM33XX_DMA_GPIO					22
+#define AM33XX_DMA_GPIO1				23
+#define AM33XX_DMA_MMCHS0_W				24
+#define AM33XX_DMA_MMCHS0_R				25
+#define AM33XX_DMA_UART0_0				26
+#define AM33XX_DMA_UART0_1				27
+#define AM33XX_DMA_UART1_0				28
+#define AM33XX_DMA_UART1_1				29
+#define AM33XX_DMA_UART2_0				30
+#define AM33XX_DMA_UART2_1				31
+#define AM33XX_DMA_DESEIP16T0_IN			32
+#define AM33XX_DMA_DESEIP16T0				33
+#define AM33XX_DMA_DESEIP16T0_OUT			34
+#define AM33XX_DMA_SHAEIP57T0_CTXIN			35
+#define AM33XX_DMA_SHAEIP57T0_DIN			36
+#define AM33XX_DMA_SHAEIP57T0_CTXOUT			37
+#define AM33XX_DMA_PWMSS0_ECAP				38
+#define AM33XX_DMA_PWMSS1_ECAP				39
+#define AM33XX_DMA_DCAN_1				40
+#define AM33XX_DMA_DCAN_2				41
+#define AM33XX_DMA_SPIOCP1_CH0W				42
+#define AM33XX_DMA_SPIOCP1_CH0R				43
+#define AM33XX_DMA_SPIOCP1_CH1W				44
+#define AM33XX_DMA_SPIOCP1_CH1R				45
+#define AM33XX_DMA_PWMSS0_EQEP				46
+#define AM33XX_DMA_DCAN_3				47
+#define AM33XX_DMA_TIMER_4				48
+#define AM33XX_DMA_TIMER_5				49
+#define AM33XX_DMA_TIMER_6				50
+#define AM33XX_DMA_TIMER_7				51
+#define AM33XX_DMA_GPM					52
+#define AM33XX_DMA_ADC0					53
+#define AM33XX_DMA_PWMSS1_EQEP				56
+#define AM33XX_DMA_ADC1					57
+#define AM33XX_DMA_MSHSI2COCP0_TX			58
+#define AM33XX_DMA_MSHSI2COCP0_RX			59
+#define AM33XX_DMA_MSHSI2COCP1_TX			60
+#define AM33XX_DMA_MSHSI2COCP1_RX			61
+#define AM33XX_DMA_PWMSS2_ECAP				62
+#define AM33XX_DMA_PWMSS2_EPW				63
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index dc562a5..c865dbc 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -30,6 +30,7 @@

 /* Move omap4 specific defines to dma-44xx.h */
 #include "dma-44xx.h"
+#include "dma-33xx.h"

 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE		0
diff --git a/arch/arm/plat-omap/include/plat/irqs-33xx.h b/arch/arm/plat-omap/include/plat/irqs-33xx.h
new file mode 100644
index 0000000..3e12d83
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs-33xx.h
@@ -0,0 +1,143 @@
+/*
+ * AM33XX interrupts.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
+#define __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H
+
+
+#define AM33XX_IRQ_ELM			4
+#define AM33XX_IRQ_PI_NMI		7
+#define AM33XX_IRQ_CONTROL_PLATFORM	8
+#define AM33XX_IRQ_L3_FLAGMUX0		9
+#define AM33XX_IRQ_L3_FLAGMUX1		10
+#define AM33XX_IRQ_PRCM			11
+#define AM33XX_IRQ_TPCC0_INT_PO0	12
+#define AM33XX_IRQ_TPCC0_MPINT_PO	13
+#define AM33XX_IRQ_TPCC0_ERRINT_PO	14
+#define AM33XX_IRQ_WDT0			15
+#define AM33XX_IRQ_ADC_GEN		16
+#define AM33XX_IRQ_USBSS		17
+#define AM33XX_IRQ_USB0			18
+#define AM33XX_IRQ_USB1			19
+#define AM33XX_IRQ_ICSS0_0		20
+#define AM33XX_IRQ_ICSS0_1		21
+#define AM33XX_IRQ_ICSS0_2		22
+#define AM33XX_IRQ_ICSS0_3		23
+#define AM33XX_IRQ_ICSS0_4		24
+#define AM33XX_IRQ_ICSS0_5		25
+#define AM33XX_IRQ_ICSS0_6		26
+#define AM33XX_IRQ_ICSS0_7		27
+#define AM33XX_IRQ_MMCHS1		28
+#define AM33XX_IRQ_MMCHS2		29
+#define AM33XX_IRQ_MSHSI2COCP2		30
+#define AM33XX_IRQ_PWMSS0_ECAP		31
+#define AM33XX_IRQ_GPIO2_1		32
+#define AM33XX_IRQ_GPIO2_2		33
+#define AM33XX_IRQ_USB_P		34
+#define AM33XX_IRQ_PCI_SLV		35
+#define AM33XX_IRQ_LCD			36
+#define AM33XX_IRQ_THALIAIRQ		37
+#define AM33XX_IRQ_BB_2DHWA		38
+#define AM33XX_IRQ_PWMSS2_EPWM		39
+#define AM33XX_IRQ_CPSW_C0_RX		40
+#define AM33XX_IRQ_CPSW_RX		41
+#define AM33XX_IRQ_CPSW_TX		42
+#define AM33XX_IRQ_CPSW_C0		43
+#define AM33XX_IRQ_UART3		44
+#define AM33XX_IRQ_UART4		45
+#define AM33XX_IRQ_UART5		46
+#define AM33XX_IRQ_PWMSS1_ECAP		47
+#define AM33XX_IRQ_PCI0			48
+#define AM33XX_IRQ_PCI1			49
+#define AM33XX_IRQ_PCI2			50
+#define AM33XX_IRQ_PCI3			51
+#define AM33XX_IRQ_DCAN0_0		52
+#define AM33XX_IRQ_DCAN0_1		53
+#define AM33XX_IRQ_DCAN0_UERR		54
+#define AM33XX_IRQ_DCAN1_0		55
+#define AM33XX_IRQ_DCAN1_1		56
+#define AM33XX_IRQ_DCAN1_UERR		57
+#define AM33XX_IRQ_PWMSS0		58
+#define AM33XX_IRQ_PWMSS1		59
+#define AM33XX_IRQ_PWMSS2		60
+#define AM33XX_IRQ_PWMSS2_ECAP		61
+#define AM33XX_IRQ_GPIO3_1		62
+#define AM33XX_IRQ_GPIO3_2		63
+#define AM33XX_IRQ_MMCHS0		64
+#define AM33XX_IRQ_MCSPIOCP0		65
+#define AM33XX_IRQ_DMTIMER0		66
+#define AM33XX_IRQ_DMTIMER1		67
+#define AM33XX_IRQ_DMTIMER2		68
+#define AM33XX_IRQ_DMTIMER3		69
+#define AM33XX_IRQ_MSHSI2COCP0		70
+#define AM33XX_IRQ_MSHSI2COCP1		71
+#define AM33XX_IRQ_UART0		72
+#define AM33XX_IRQ_UART1		73
+#define AM33XX_IRQ_UART2		74
+#define AM33XX_IRQ_RTC_TIMER		75
+#define AM33XX_IRQ_RTC_ALARM		76
+#define AM33XX_IRQ_MAILBOX		77
+#define AM33XX_IRQ_M3_M3SP_TXEV		78
+#define AM33XX_IRQ_PWMSS0_EQEP		79
+#define AM33XX_IRQ_MCASP0_AX		80
+#define AM33XX_IRQ_MCASP0_AR		81
+#define AM33XX_IRQ_MCASP1_AX		82
+#define AM33XX_IRQ_MCASP1_AR		83
+#define AM33XX_IRQ_MCASP2_X		84
+#define AM33XX_IRQ_MCASP2_R		85
+#define AM33XX_IRQ_PWMSS0_EPWM		86
+#define AM33XX_IRQ_PWMSS1_EPWM		87
+#define AM33XX_IRQ_PWMSS1_EQEP		88
+#define AM33XX_IRQ_PWMSS2_EQEP		89
+#define AM33XX_IRQ_DMA			90
+#define AM33XX_IRQ_WDT1			91
+#define AM33XX_IRQ_DMTIMER4		92
+#define AM33XX_IRQ_DMTIMER5		93
+#define AM33XX_IRQ_DMTIMER6		94
+#define AM33XX_IRQ_DMTIMER7		95
+#define AM33XX_IRQ_GPIO0_1		96
+#define AM33XX_IRQ_GPIO0_2		97
+#define AM33XX_IRQ_GPIO1_1		98
+#define AM33XX_IRQ_GPIO1_2		99
+#define AM33XX_IRQ_GPMC0		100
+#define AM33XX_IRQ_EMI			101
+#define AM33XX_IRQ_AESEIP36t0_S		102
+#define AM33XX_IRQ_AESEIP36t0_P		103
+#define AM33XX_IRQ_AESEIP36t1_S		104
+#define AM33XX_IRQ_AESEIP36t1_P		105
+#define AM33XX_IRQ_DESEIP16t0_S		106
+#define AM33XX_IRQ_DESEIP16t0_P		107
+#define AM33XX_IRQ_SHAEIP57t0_S		108
+#define AM33XX_IRQ_SHAEIP57t0_P		109
+#define AM33XX_IRQ_PKAEIP29t0_S		110
+#define AM33XX_IRQ_RNGEIP75t0		111
+#define AM33XX_IRQ_TPTC0		112
+#define AM33XX_IRQ_TPTC1		113
+#define AM33XX_IRQ_TPTC2		114
+#define AM33XX_IRQ_TSC			115
+#define AM33XX_IRQ_SDMA0		116
+#define AM33XX_IRQ_SDMA1		117
+#define AM33XX_IRQ_SDMA2		118
+#define AM33XX_IRQ_SDMA3		119
+#define AM33XX_IRQ_SMARTREFLEX0		120
+#define AM33XX_IRQ_SMARTREFLEX1		121
+#define AM33XX_IRQ_NETRA_MMU		122
+#define AM33XX_IRQ_DMA0			123
+#define AM33XX_IRQ_DMA1			124
+#define AM33XX_IRQ_SPI1			125
+#define AM33XX_IRQ_SPI2			126
+#define AM33XX_IRQ_SPI			127
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 30e1071..29b2032 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -30,6 +30,7 @@

 /* All OMAP4 specific defines are moved to irqs-44xx.h */
 #include "irqs-44xx.h"
+#include "irqs-33xx.h"

 /*
  * IRQ numbers for interrupt handler 1
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index e988c92..ec66b42 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -61,6 +61,11 @@

 /* AM33XX serial port */
 #define AM33XX_UART1_BASE	0x44E09000
+#define AM33XX_UART2_BASE	0x48022000
+#define AM33XX_UART3_BASE	0x48024000
+#define AM33XX_UART4_BASE	0x481A6000
+#define AM33XX_UART5_BASE	0x481A8000
+#define AM33XX_UART6_BASE	0x481AA000

 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE		0x10000000
--
1.7.0.4

[RFC PATCH 07/11] arm:omap:am33xx: Add irq, dma and module base addr to SoC header files

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> This patch creats seperate irq and dma defination header file
> and updates the module base addresses required for HWMOD data.
>
> Signed-off-by: Afzal Mohammed <afzal@ti.com>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

These headers/defines should no longer be needed.  Instead, as with
OMAP4, the raw values are used in the hwmod data (and we'll be moving
device tree for these values.)

Kevin

[RFC PATCH 07/11] arm:omap:am33xx: Add irq, dma and module base addr to SoC header files

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 7:16 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit; Mohammed, Afzal
> Subject: Re: [RFC PATCH 07/11] arm:omap:am33xx: Add irq, dma and module
> base addr to SoC header files
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > This patch creats seperate irq and dma defination header file
> > and updates the module base addresses required for HWMOD data.
> >
> > Signed-off-by: Afzal Mohammed <afzal@ti.com>
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> These headers/defines should no longer be needed.  Instead, as with
> OMAP4, the raw values are used in the hwmod data (and we'll be moving
> device tree for these values.)
> 
Ok, will clean this up in next version.

Thanks,
Vaibhav

> Kevin

[RFC PATCH 08/11] arm:omap:am33xx: Add HWMOD data

[Vaibhav Hiremath]

This patch adds HWMOD data for all the peripherals of AM335X.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Rachna Patil <rachna@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c   | 2474 ++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    1 +
 2 files changed, 2475 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 0000000..b1a34ff
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,2474 @@
+/*
+ * Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/mcspi.h>
+
+#include "omap_hwmod_common_data.h"
+#include "control.h"
+#include "cm33xx.h"
+
+/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod am33xx_mpu_hwmod;
+static struct omap_hwmod am33xx_l3slow_hwmod;
+static struct omap_hwmod am33xx_l4wkup_hwmod;
+static struct omap_hwmod am33xx_l4per_hwmod;
+static struct omap_hwmod am33xx_uart1_hwmod;
+static struct omap_hwmod am33xx_uart2_hwmod;
+static struct omap_hwmod am33xx_uart3_hwmod;
+static struct omap_hwmod am33xx_uart4_hwmod;
+static struct omap_hwmod am33xx_uart5_hwmod;
+static struct omap_hwmod am33xx_uart6_hwmod;
+static struct omap_hwmod am33xx_timer0_hwmod;
+static struct omap_hwmod am33xx_timer1_hwmod;
+static struct omap_hwmod am33xx_timer2_hwmod;
+static struct omap_hwmod am33xx_timer3_hwmod;
+static struct omap_hwmod am33xx_timer4_hwmod;
+static struct omap_hwmod am33xx_timer5_hwmod;
+static struct omap_hwmod am33xx_timer6_hwmod;
+static struct omap_hwmod am33xx_timer7_hwmod;
+static struct omap_hwmod am33xx_wd_timer1_hwmod;
+static struct omap_hwmod am33xx_cpgmac0_hwmod;
+static struct omap_hwmod am33xx_icss_hwmod;
+static struct omap_hwmod am33xx_ieee5000_hwmod;
+static struct omap_hwmod am33xx_tptc0_hwmod;
+static struct omap_hwmod am33xx_tptc1_hwmod;
+static struct omap_hwmod am33xx_tptc2_hwmod;
+static struct omap_hwmod am33xx_gpio0_hwmod;
+static struct omap_hwmod am33xx_gpio1_hwmod;
+static struct omap_hwmod am33xx_gpio2_hwmod;
+static struct omap_hwmod am33xx_gpio3_hwmod;
+static struct omap_hwmod am33xx_i2c1_hwmod;
+static struct omap_hwmod am33xx_i2c2_hwmod;
+static struct omap_hwmod am33xx_usbss_hwmod;
+static struct omap_hwmod am33xx_mmc0_hwmod;
+static struct omap_hwmod am33xx_mmc1_hwmod;
+static struct omap_hwmod am33xx_mmc2_hwmod;
+static struct omap_hwmod am33xx_spi0_hwmod;
+static struct omap_hwmod am33xx_spi1_hwmod;
+
+/*
+ * Interconnects hwmod structures
+ * hwmods that compose the global AM33XX OCP interconnect
+ */
+
+/* MPU -> L3_SLOW Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
+	.master 	= &am33xx_mpu_hwmod,
+	.slave		= &am33xx_l3slow_hwmod,
+	.user		= OCP_USER_MPU,
+};
+
+/* L3 SLOW -> L4_PER Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
+	.master 	= &am33xx_l3slow_hwmod,
+	.slave		= &am33xx_l4per_hwmod,
+	.user		= OCP_USER_MPU,
+};
+
+/* L3 SLOW -> L4_WKUP Peripheral interface */
+static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
+	.master 	= &am33xx_l3slow_hwmod,
+	.slave		= &am33xx_l4wkup_hwmod,
+	.user		= OCP_USER_MPU,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
+	&am33xx_l3_slow__l4_per,
+	&am33xx_l3_slow__l4_wkup,
+};
+
+/* Slave interfaces on the L3_SLOW interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
+	&am33xx_mpu__l3_slow,
+};
+
+static struct omap_hwmod am33xx_l3slow_hwmod = {
+	.name		= "l3_slow",
+	.class		= &l3_hwmod_class,
+	.clkdm_name	= "l3s_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.masters	= am33xx_l3_slow_masters,
+	.masters_cnt	= ARRAY_SIZE(am33xx_l3_slow_masters),
+	.slaves		= am33xx_l3_slow_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_l3_slow_slaves),
+};
+
+/* L4 PER -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+	{
+		.pa_start	= AM33XX_GPIO1_BASE,
+		.pa_end		= AM33XX_GPIO1_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_gpio1_hwmod,
+	.clk		= "l4ls_fck",
+	.addr		= am33xx_gpio1_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> GPIO3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+	{
+		.pa_start	= AM33XX_GPIO2_BASE,
+		.pa_end		= AM33XX_GPIO2_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_gpio2_hwmod,
+	.clk		= "l4ls_fck",
+	.addr		= am33xx_gpio2_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> GPIO4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+	{
+		.pa_start	= AM33XX_GPIO3_BASE,
+		.pa_end		= AM33XX_GPIO3_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_gpio3_hwmod,
+	.clk		= "l4ls_fck",
+	.addr		= am33xx_gpio3_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Master interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
+	&am33xx_l4_per__gpio1,
+	&am33xx_l4_per__gpio2,
+	&am33xx_l4_per__gpio3,
+};
+/* Slave interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
+	&am33xx_l3_slow__l4_per,
+};
+
+static struct omap_hwmod am33xx_l4per_hwmod = {
+	.name		= "l4_per",
+	.class		= &l4_hwmod_class,
+	.clkdm_name	= "l4ls_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.masters	= am33xx_l4_per_masters,
+	.masters_cnt	= ARRAY_SIZE(am33xx_l4_per_masters),
+	.slaves		= am33xx_l4_per_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_per_slaves),
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+	{
+		.pa_start	= AM33XX_I2C0_BASE,
+		.pa_end		= AM33XX_I2C0_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_i2c1_hwmod,
+	.addr		= am33xx_i2c1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+	{
+		.pa_start	= AM33XX_GPIO0_BASE,
+		.pa_end		= AM33XX_GPIO0_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_gpio0_hwmod,
+	.clk		= "l4ls_fck",
+	.addr		= am33xx_gpio0_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
+	&am33xx_l4_wkup__gpio0,
+};
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
+	&am33xx_l3_slow__l4_wkup,
+};
+
+static struct omap_hwmod am33xx_l4wkup_hwmod = {
+	.name		= "l4_wkup",
+	.class		= &l4_hwmod_class,
+	.clkdm_name	= "l4_wkup_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.masters	= am33xx_l4_wkup_masters,
+	.masters_cnt	= ARRAY_SIZE(am33xx_l4_wkup_masters),
+	.slaves		= am33xx_l4_wkup_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_l4_wkup_slaves),
+};
+
+/* 'adc_tsc' class */
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+	.name		= "adc_tsc",
+};
+
+/* adc_tsc */
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+	{ .irq = AM33XX_IRQ_TSC },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+	.name		= "adc_tsc",
+	.class		= &am33xx_adc_tsc_hwmod_class,
+	.mpu_irqs	= am33xx_adc_tsc_irqs,
+	.main_clk	= "adc_tsc_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'aes' class */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+	.name		= "aes",
+};
+
+/* aes0 */
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+	{ .irq = AM33XX_IRQ_AESEIP36t0_S },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+	.name		= "aes0",
+	.class		= &am33xx_aes_hwmod_class,
+	.mpu_irqs	= am33xx_aes0_irqs,
+	.main_clk	= "aes0_fck",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'cefuse' class */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+	.name		= "cefuse",
+};
+
+/* cefuse */
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+	.name		= "cefuse",
+	.class		= &am33xx_cefuse_hwmod_class,
+	.main_clk	= "cefuse_fck",
+	.clkdm_name	= "l4_cefuse_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'clkdiv32k' class */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+	.name		= "clkdiv32k",
+};
+
+/* clkdiv32k */
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+	.name		= "clkdiv32k",
+	.class		= &am33xx_clkdiv32k_hwmod_class,
+	.main_clk	= "clkdiv32k_fck",
+	.clkdm_name	= "clk_24mhz_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+};
+
+/* 'control' class */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+	.name		= "control",
+};
+
+/* control */
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+	{ .irq = AM33XX_IRQ_CONTROL_PLATFORM },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+	.name		= "control",
+	.class		= &am33xx_control_hwmod_class,
+	.mpu_irqs	= am33xx_control_irqs,
+	.main_clk	= "control_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+};
+
+/* 'cpgmac0' class */
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+	.name		= "cpgmac0",
+};
+
+/* cpgmac0 */
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+	.name		= "cpgmac0",
+	.class		= &am33xx_cpgmac0_hwmod_class,
+	.main_clk	= "cpgmac0_fck",
+	.clkdm_name	= "cpsw_125mhz_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'dcan' class */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+	.name		= "dcan",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+	{ .irq = AM33XX_IRQ_DCAN0_0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+	.name		= "dcan0",
+	.class		= &am33xx_dcan_hwmod_class,
+	.mpu_irqs	= am33xx_dcan0_irqs,
+	.main_clk	= "dcan0_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+	{ .irq = AM33XX_IRQ_DCAN1_0 },
+	{ .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+	.name		= "dcan1",
+	.class		= &am33xx_dcan_hwmod_class,
+	.mpu_irqs	= am33xx_dcan1_irqs,
+	.main_clk	= "dcan1_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'debugss' class */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+	.name		= "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod am33xx_debugss_hwmod = {
+	.name		= "debugss",
+	.class		= &am33xx_debugss_hwmod_class,
+	.main_clk	= "debugss_fck",
+	.clkdm_name	= "l3_aon_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'elm' class */
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+	.name		= "elm",
+};
+
+/* elm */
+static struct omap_hwmod am33xx_elm_hwmod = {
+	.name		= "elm",
+	.class		= &am33xx_elm_hwmod_class,
+	.main_clk	= "elm_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'emif_fw' class */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+	.name		= "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+	.name		= "emif_fw",
+	.class		= &am33xx_emif_fw_hwmod_class,
+	.main_clk	= "emif_fw_fck",
+	.clkdm_name	= "l4fw_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.flags		= HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
+};
+
+/* 'epwmss' class */
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+	.name		= "epwmss",
+};
+
+/* epwmss0 */
+static struct omap_hwmod am33xx_epwmss0_hwmod = {
+	.name		= "epwmss0",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.main_clk	= "epwmss0_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* epwmss1 */
+static struct omap_hwmod am33xx_epwmss1_hwmod = {
+	.name		= "epwmss1",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.main_clk	= "epwmss1_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* epwmss2 */
+static struct omap_hwmod am33xx_epwmss2_hwmod = {
+	.name		= "epwmss2",
+	.class		= &am33xx_epwmss_hwmod_class,
+	.main_clk	= "epwmss2_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0114,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+			SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+/* 'gpio' class */
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+	.name		= "gpio",
+	.sysc		= &am33xx_gpio_sysc,
+	.rev		= 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+	.bank_width	= 32,
+	.dbck_flag	= true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+	{ .irq = AM33XX_IRQ_GPIO0_1 },
+	{ .irq = -1 },
+};
+
+/* gpio0 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
+	&am33xx_l4_wkup__gpio0,
+};
+
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+/* gpio0 */
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+	.name		= "gpio1",
+	.class		= &am33xx_gpio_hwmod_class,
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= am33xx_gpio0_irqs,
+	.main_clk	= "gpio0_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= gpio0_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+	.slaves		= am33xx_gpio0_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio0_slaves),
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+	{ .irq = AM33XX_IRQ_GPIO1_1 },
+	{ .irq = -1 },
+};
+
+/* gpio1 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
+	&am33xx_l4_per__gpio1,
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+	.name		= "gpio2",
+	.class		= &am33xx_gpio_hwmod_class,
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= am33xx_gpio1_irqs,
+	.main_clk	= "gpio1_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= gpio1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+	.slaves		= am33xx_gpio1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio1_slaves),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+	{ .irq = AM33XX_IRQ_GPIO2_1 },
+	{ .irq = -1 },
+};
+
+/* gpio2 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
+	&am33xx_l4_per__gpio2,
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+/* gpio2 */
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+	.name		= "gpio3",
+	.class		= &am33xx_gpio_hwmod_class,
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= am33xx_gpio2_irqs,
+	.main_clk	= "gpio2_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= gpio2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+	.slaves		= am33xx_gpio2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio2_slaves),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+	{ .irq = AM33XX_IRQ_GPIO3_1 },
+	{ .irq = -1 },
+};
+
+/* gpio3 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
+	&am33xx_l4_per__gpio3,
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+	{ .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+/* gpio3 */
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+	.name		= "gpio4",
+	.class		= &am33xx_gpio_hwmod_class,
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= am33xx_gpio3_irqs,
+	.main_clk	= "gpio3_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= gpio3_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
+	.dev_attr	= &gpio_dev_attr,
+	.slaves		= am33xx_gpio3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_gpio3_slaves),
+};
+
+/* 'gpmc' class */
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+	.name		= "gpmc",
+};
+
+/* gpmc */
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+	.name		= "gpmc",
+	.class		= &am33xx_gpmc_hwmod_class,
+	.main_clk	= "gpmc_fck",
+	.clkdm_name	= "l3s_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'i2c' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0090,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+			SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+static struct omap_hwmod_class i2c_class = {
+	.name		= "i2c",
+	.sysc		= &am33xx_i2c_sysc,
+	.rev		= OMAP_I2C_IP_VERSION_2,
+	.reset		= &omap_i2c_reset,
+};
+
+/* I2C1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+	{ .irq = AM33XX_IRQ_MSHSI2COCP0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+	{ .name = "tx", .dma_req = 0, },
+	{ .name = "rx", .dma_req = 0, },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
+	&am33xx_l4_wkup_i2c1,
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+	.name		= "i2c1",
+	.mpu_irqs	= i2c1_mpu_irqs,
+	.sdma_reqs	= i2c1_edma_reqs,
+	.main_clk	= "i2c1_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.flags		= HWMOD_16BIT_REG,
+	.dev_attr	= &i2c_dev_attr,
+	.slaves		= am33xx_i2c1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c1_slaves),
+	.class		= &i2c_class,
+};
+
+/* i2c2 */
+/* l4 per -> i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+	{
+		.pa_start	= AM33XX_I2C1_BASE,
+		.pa_end		= AM33XX_I2C1_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_i2c2_hwmod,
+	.addr		= am33xx_i2c2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+	{ .irq = AM33XX_IRQ_MSHSI2COCP1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+	{ .name = "tx", .dma_req = 0, },
+	{ .name = "rx", .dma_req = 0, },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
+	&am335_l4_per_i2c2,
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+	.name		= "i2c2",
+	.mpu_irqs	= i2c2_mpu_irqs,
+	.sdma_reqs	= i2c2_edma_reqs,
+	.main_clk	= "i2c2_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4 = {
+			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.flags		= HWMOD_16BIT_REG,
+	.dev_attr	= &i2c_dev_attr,
+	.slaves		= am33xx_i2c2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_i2c2_slaves),
+	.class		= &i2c_class,
+};
+
+/* 'icss' class */
+static struct omap_hwmod_class am33xx_icss_hwmod_class = {
+	.name = "icss",
+};
+
+/* icss */
+static struct omap_hwmod am33xx_icss_hwmod = {
+	.name		= "icss",
+	.class		= &am33xx_icss_hwmod_class,
+	.main_clk	= "icss_fck",
+	.clkdm_name	= "icss_ocp_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'ieee5000' class */
+static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
+	.name		= "ieee5000",
+};
+
+/* ieee5000 */
+static struct omap_hwmod am33xx_ieee5000_hwmod = {
+	.name		= "ieee5000",
+	.class		= &am33xx_ieee5000_hwmod_class,
+	.main_clk	= "ieee5000_fck",
+	.clkdm_name	= "l3s_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+
+/* 'l3' class */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+	.name		= "l3",
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+	.name		= "l4_hs",
+	.class		= &am33xx_l3_hwmod_class,
+	.clkdm_name	= "l4hs_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+	.name		= "l3_instr",
+	.class		= &am33xx_l3_hwmod_class,
+	.clkdm_name	= "l3_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* l3_main */
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+	.name		= "l3_main",
+	.class		= &am33xx_l3_hwmod_class,
+	.clkdm_name	= "l3_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'l4fw' class */
+static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
+	.name		= "l4fw",
+};
+
+/* l4fw */
+static struct omap_hwmod am33xx_l4fw_hwmod = {
+	.name		= "l4fw",
+	.class		= &am33xx_l4fw_hwmod_class,
+	.clkdm_name	= "l4fw_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'l4ls' class */
+static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
+	.name		= "l4ls",
+};
+
+/* l4ls */
+static struct omap_hwmod am33xx_l4ls_hwmod = {
+	.name		= "l4ls",
+	.class		= &am33xx_l4ls_hwmod_class,
+	.main_clk	= "l4ls_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'lcdc' class */
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+	.name		= "lcdc",
+};
+
+/* lcdc */
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+	{ .irq = AM33XX_IRQ_LCD },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+	.name		= "lcdc",
+	.class		= &am33xx_lcdc_hwmod_class,
+	.mpu_irqs	= am33xx_lcdc_irqs,
+	.main_clk	= "lcdc_fck",
+	.clkdm_name	= "lcdc_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'mcasp' class */
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+	.name		= "mcasp",
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+	{ .irq = 80 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+	.name		= "mcasp0",
+	.class		= &am33xx_mcasp_hwmod_class,
+	.mpu_irqs	= am33xx_mcasp0_irqs,
+	.main_clk	= "mcasp0_fck",
+	.clkdm_name	= "l3s_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'mmc' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+	.rev_offs	= 0x1fc,
+	.sysc_offs	= 0x10,
+	.syss_offs	= 0x14,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+			SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+	.name		= "mmc",
+	.sysc		= &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+	{ .irq = AM33XX_IRQ_MMCHS0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+	{
+		.pa_start	= AM33XX_MMC0_BASE,
+		.pa_end		= AM33XX_MMC0_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
+	.master		= &am33xx_l4ls_hwmod,
+	.slave		= &am33xx_mmc0_hwmod,
+	.clk		= "mmc0_ick",
+	.addr		= am33xx_mmc0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
+	&am33xx_l4ls__mmc0,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+	.name		= "mmc1",
+	.class		= &am33xx_mmc_hwmod_class,
+	.mpu_irqs	= am33xx_mmc0_irqs,
+	.main_clk	= "mmc0_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &am33xx_mmc0_dev_attr,
+	.slaves		= am33xx_mmc0_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc0_slaves),
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+	{ .irq = AM33XX_IRQ_MMCHS1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+	{
+		.pa_start	= AM33XX_MMC1_BASE,
+		.pa_end		= AM33XX_MMC1_BASE + SZ_4K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
+	.master		= &am33xx_l4ls_hwmod,
+	.slave		= &am33xx_mmc1_hwmod,
+	.clk		= "mmc1_ick",
+	.addr		= am33xx_mmc1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
+	&am33xx_l4ls__mmc1,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+	.name		= "mmc2",
+	.class		= &am33xx_mmc_hwmod_class,
+	.mpu_irqs	= am33xx_mmc1_irqs,
+	.main_clk	= "mmc1_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &am33xx_mmc1_dev_attr,
+	.slaves		= am33xx_mmc1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc1_slaves),
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+	{ .irq = AM33XX_IRQ_MMCHS2 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+	{
+		.pa_start	= AM33XX_MMC2_BASE,
+		.pa_end		= AM33XX_MMC2_BASE + SZ_64K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
+	.master		= &am33xx_l3_main_hwmod,
+	.slave		= &am33xx_mmc2_hwmod,
+	.clk		= "mmc2_ick",
+	.addr		= am33xx_mmc2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
+	&am33xx_l3_main__mmc2,
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+	.flags		= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+	.name		= "mmc3",
+	.class		= &am33xx_mmc_hwmod_class,
+	.mpu_irqs	= am33xx_mmc2_irqs,
+	.main_clk	= "mmc2_fck",
+	.clkdm_name	= "l3s_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &am33xx_mmc2_dev_attr,
+	.slaves		= am33xx_mmc2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_mmc2_slaves),
+};
+
+/* Master interfaces on the MPU interconnect */
+static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
+	&am33xx_mpu__l3_slow,
+};
+
+/* mpu */
+static struct omap_hwmod am33xx_mpu_hwmod = {
+	.name		= "mpu",
+	.class		= &mpu_hwmod_class,
+	.masters	= am33xx_l3_mpu_masters,
+	.masters_cnt	= ARRAY_SIZE(am33xx_l3_mpu_masters),
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.main_clk	= "mpu_fck",
+	.clkdm_name	= "mpu_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'ocmcram' class */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+	.name = "ocmcram",
+};
+
+/* ocmcram */
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+	.name		= "ocmcram",
+	.class		= &am33xx_ocmcram_hwmod_class,
+	.main_clk	= "ocmcram_fck",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'ocpwp' class */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+	.name		= "ocpwp",
+};
+
+/* ocpwp */
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+	.name		= "ocpwp",
+	.class		= &am33xx_ocpwp_hwmod_class,
+	.main_clk	= "ocpwp_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'rtc' class */
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+	.name		= "rtc",
+};
+
+/* rtc */
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+	{ .irq = AM33XX_IRQ_RTC_TIMER },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+	.name		= "rtc",
+	.class		= &am33xx_rtc_hwmod_class,
+	.mpu_irqs	= am33xx_rtc_irqs,
+	.main_clk	= "rtc_fck",
+	.clkdm_name	= "l4_rtc_clkdm",
+	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'sha0' class */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+	.name		= "sha0",
+};
+
+/* sha0 */
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+	{ .irq = AM33XX_IRQ_SHAEIP57t0_S },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+	.name		= "sha0",
+	.class		= &am33xx_sha0_hwmod_class,
+	.mpu_irqs	= am33xx_sha0_irqs,
+	.main_clk	= "sha0_fck",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+	.name		= "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+	{ .irq = AM33XX_IRQ_SMARTREFLEX0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+	.name		= "smartreflex0",
+	.class		= &am33xx_smartreflex_hwmod_class,
+	.mpu_irqs	= am33xx_smartreflex0_irqs,
+	.main_clk	= "smartreflex0_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+	{ .irq = AM33XX_IRQ_SMARTREFLEX1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+	.name		= "smartreflex1",
+	.class		= &am33xx_smartreflex_hwmod_class,
+	.mpu_irqs	= am33xx_smartreflex1_irqs,
+	.main_clk	= "smartreflex1_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'spi' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0110,
+	.syss_offs	= 0x0114,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+	.name		= "mcspi",
+	.sysc		= &am33xx_mcspi_sysc,
+	.rev		= OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+	{ .irq = AM33XX_IRQ_MCSPIOCP0 },
+	{ .irq = -1 },
+};
+
+struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+	{
+		.pa_start	= AM33XX_SPI0_BASE,
+		.pa_end		= AM33XX_SPI0_BASE + SZ_1K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+	{ },
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_spi0_hwmod,
+	.clk		= "spi0_ick",
+	.addr		= am33xx_mcspi0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
+	&am33xx_l4_core__mcspi0,
+};
+
+struct omap2_mcspi_dev_attr mcspi_attrib = {
+	.num_chipselect	= 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+	.name		= "spi0",
+	.class		= &am33xx_spi_hwmod_class,
+	.mpu_irqs	= am33xx_spi0_irqs,
+	.main_clk	= "spi0_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi_attrib,
+	.slaves		= am33xx_mcspi0_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi0_slaves),
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+	{ .irq = AM33XX_IRQ_SPI1 },
+	{ .irq = -1 },
+};
+
+struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+	{
+		.pa_start	= AM33XX_SPI1_BASE,
+		.pa_end		= AM33XX_SPI1_BASE + SZ_1K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+	{ },
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_spi1_hwmod,
+	.clk		= "spi1_ick",
+	.addr		= am33xx_mcspi1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
+	&am33xx_l4_core__mcspi1,
+};
+static struct omap_hwmod am33xx_spi1_hwmod = {
+	.name		= "spi1",
+	.class		= &am33xx_spi_hwmod_class,
+	.mpu_irqs	= am33xx_spi1_irqs,
+	.main_clk	= "spi1_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.dev_attr	= &mcspi_attrib,
+	.slaves		= am33xx_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_mcspi1_slaves),
+};
+
+/* 'spinlock' class */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+	.name		= "spinlock",
+};
+
+/* spinlock */
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+	.name		= "spinlock",
+	.class		= &am33xx_spinlock_hwmod_class,
+	.main_clk	= "spinlock_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'timer 0 & 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+	.name		= "timer",
+	.sysc		= &am33xx_timer_sysc,
+};
+
+/* timer0 */
+/* l4 wkup -> timer0 interface */
+static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER0_BASE,
+		.pa_end		= AM33XX_TIMER0_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_timer0_hwmod,
+	.clk		= "timer0_ick",
+	.addr		= am33xx_timer0_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
+	&am33xx_l4wkup__timer0,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer0_hwmod = {
+	.name		= "timer0",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer0_irqs,
+	.main_clk	= "timer0_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer0_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer0_slaves),
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+			SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+	.name		= "timer",
+	.sysc		= &am33xx_timer1ms_sysc,
+};
+
+/* l4 wkup -> timer1 interface */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER1_BASE,
+		.pa_end		= AM33XX_TIMER1_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_timer1_hwmod,
+	.clk		= "timer1_ick",
+	.addr		= am33xx_timer1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
+	&am33xx_l4wkup__timer1,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+	.name		= "timer1",
+	.class		= &am33xx_timer1ms_hwmod_class,
+	.mpu_irqs	= am33xx_timer1_irqs,
+	.main_clk	= "timer1_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer1_slaves),
+};
+
+/* timer2 */
+/* l4 per -> timer2 interface */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER2_BASE,
+		.pa_end		= AM33XX_TIMER2_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer2_hwmod,
+	.clk		= "timer2_ick",
+	.addr		= am33xx_timer2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
+	&am33xx_l4per__timer2,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER2 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+	.name		= "timer2",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer2_irqs,
+	.main_clk	= "timer2_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer2_slaves),
+	.clkdm_name	= "l4ls_clkdm",
+};
+
+/* timer3 */
+/* l4 per -> timer3 interface */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER3_BASE,
+		.pa_end		= AM33XX_TIMER3_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer3_hwmod,
+	.clk		= "timer3_ick",
+	.addr		= am33xx_timer3_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
+	&am33xx_l4per__timer3,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER3 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+	.name		= "timer3",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer3_irqs,
+	.main_clk	= "timer3_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer3_slaves),
+};
+
+/* timer4 */
+/* l4 per -> timer4 interface */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER4_BASE,
+		.pa_end		= AM33XX_TIMER4_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer4_hwmod,
+	.clk		= "timer4_ick",
+	.addr		= am33xx_timer4_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
+	&am33xx_l4per__timer4,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER4 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+	.name		= "timer4",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer4_irqs,
+	.main_clk	= "timer4_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer4_slaves),
+	.clkdm_name	= "l4ls_clkdm",
+};
+
+
+/* timer5 */
+/* l4 per -> timer5 interface */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER5_BASE,
+		.pa_end		= AM33XX_TIMER5_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer5_hwmod,
+	.clk		= "timer5_ick",
+	.addr		= am33xx_timer5_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
+	&am33xx_l4per__timer5,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER5 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+	.name		= "timer5",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer5_irqs,
+	.main_clk	= "timer5_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer5_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer5_slaves),
+	.clkdm_name	= "l4ls_clkdm",
+};
+
+/* timer6 */
+/* l4 per -> timer6 interface */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER6_BASE,
+		.pa_end		= AM33XX_TIMER6_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer6_hwmod,
+	.clk		= "timer6_ick",
+	.addr		= am33xx_timer6_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
+	&am33xx_l4per__timer6,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER6 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+	.name		= "timer6",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer6_irqs,
+	.main_clk	= "timer6_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer6_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer6_slaves),
+	.clkdm_name	= "l4ls_clkdm",
+};
+
+/* timer7 */
+/* l4 per -> timer7 interface */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+	{
+		.pa_start	= AM33XX_TIMER7_BASE,
+		.pa_end		= AM33XX_TIMER7_BASE + SZ_1K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
+	.master		= &am33xx_l4per_hwmod,
+	.slave		= &am33xx_timer7_hwmod,
+	.clk		= "timer7_ick",
+	.addr		= am33xx_timer7_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
+	&am33xx_l4per__timer7,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+	{ .irq = AM33XX_IRQ_DMTIMER7 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+	.name		= "timer7",
+	.class		= &am33xx_timer_hwmod_class,
+	.mpu_irqs	= am33xx_timer7_irqs,
+	.main_clk	= "timer7_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_timer7_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_timer7_slaves),
+	.clkdm_name	= "l4ls_clkdm",
+};
+
+/* 'tpcc' class */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+	.name		= "tpcc",
+};
+
+/* tpcc */
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+	{ .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+	.name		= "tpcc",
+	.class		= &am33xx_tpcc_hwmod_class,
+	.mpu_irqs	= am33xx_tpcc_irqs,
+	.main_clk	= "tpcc_ick",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+	.name		= "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+	{ .irq = AM33XX_IRQ_TPTC0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+	.name		= "tptc0",
+	.class		= &am33xx_tptc_hwmod_class,
+	.mpu_irqs	= am33xx_tptc0_irqs,
+	.main_clk	= "tptc0_ick",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+	{ .irq = AM33XX_IRQ_TPTC1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+	.name		= "tptc1",
+	.class		= &am33xx_tptc_hwmod_class,
+	.mpu_irqs	= am33xx_tptc1_irqs,
+	.main_clk	= "tptc1_ick",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+	{ .irq = AM33XX_IRQ_TPTC2 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+	.name		= "tptc2",
+	.class		= &am33xx_tptc_hwmod_class,
+	.mpu_irqs	= am33xx_tptc2_irqs,
+	.main_clk	= "tptc2_ick",
+	.clkdm_name	= "l3_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+	.rev_offs	= 0x50,
+	.sysc_offs	= 0x54,
+	.syss_offs	= 0x58,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
+			SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+			SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+	.name		= "uart",
+	.sysc		= &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+	{ .name = "tx",	.dma_req = 26, },
+	{ .name = "rx",	.dma_req = 27, },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART1_BASE,
+		.pa_end		= AM33XX_UART1_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_uart1_hwmod,
+	.clk		= "uart1_ick",
+	.addr		= am33xx_uart1_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART0 },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
+	&am33xx_l4_wkup__uart1,
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+	.name		= "uart1",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart1_irqs,
+	.sdma_reqs	= uart1_edma_reqs,
+	.main_clk	= "uart1_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart1_slaves),
+};
+
+/* uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART2_BASE,
+		.pa_end		= AM33XX_UART2_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+	.slave		= &am33xx_uart2_hwmod,
+	.clk		= "uart2_ick",
+	.addr		= am33xx_uart2_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART1 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
+	&am33xx_l4_ls__uart2,
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+	.name		= "uart2",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart2_irqs,
+	.main_clk	= "uart2_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.sdma_reqs	= uart1_edma_reqs,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart2_slaves),
+};
+
+/* uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART3_BASE,
+		.pa_end		= AM33XX_UART3_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+	.slave		= &am33xx_uart3_hwmod,
+	.clk		= "uart3_ick",
+	.addr		= am33xx_uart3_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART2 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
+	&am33xx_l4_ls__uart3,
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+	.name		= "uart3",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart3_irqs,
+	.main_clk	= "uart3_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.sdma_reqs	= uart1_edma_reqs,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart3_slaves),
+};
+
+/* uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART4_BASE,
+		.pa_end		= AM33XX_UART4_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+	.slave		= &am33xx_uart4_hwmod,
+	.clk		= "uart4_ick",
+	.addr		= am33xx_uart4_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART3 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
+	&am33xx_l4_ls__uart4,
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+	.name		= "uart4",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart4_irqs,
+	.main_clk	= "uart4_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.sdma_reqs	= uart1_edma_reqs,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart4_slaves),
+};
+
+/* uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART5_BASE,
+		.pa_end		= AM33XX_UART5_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+	.slave		= &am33xx_uart5_hwmod,
+	.clk		= "uart5_ick",
+	.addr		= am33xx_uart5_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART4 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
+	&am33xx_l4_ls__uart5,
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+	.name		= "uart5",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart5_irqs,
+	.main_clk	= "uart5_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.sdma_reqs	= uart1_edma_reqs,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart5_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart5_slaves),
+};
+
+/* uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+	{
+		.pa_start	= AM33XX_UART6_BASE,
+		.pa_end		= AM33XX_UART6_BASE + SZ_8K - 1,
+		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+	.slave		= &am33xx_uart6_hwmod,
+	.clk		= "uart6_ick",
+	.addr		= am33xx_uart6_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+	{ .irq = AM33XX_IRQ_UART5 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
+	&am33xx_l4_ls__uart6,
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+	.name		= "uart6",
+	.class		= &uart_class,
+	.mpu_irqs	= am33xx_uart6_irqs,
+	.main_clk	= "uart6_fck",
+	.clkdm_name	= "l4ls_clkdm",
+	.sdma_reqs	= uart1_edma_reqs,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_uart6_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_uart6_slaves),
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+	.name		= "wd_timer",
+};
+
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+	{
+		.pa_start	= AM33XX_WDT1_BASE,
+		.pa_end		= AM33XX_WDT1_BASE + SZ_4K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ },
+};
+
+/* l4_wkup -> wd_timer1 */
+static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
+	.master		= &am33xx_l4wkup_hwmod,
+	.slave		= &am33xx_wd_timer1_hwmod,
+	.addr		= am33xx_wd_timer1_addrs,
+	.user		= OCP_USER_MPU,
+};
+
+/* wd_timer1 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
+	&am33xx_l4wkup__wd_timer1,
+};
+
+/* wd_timer1 */
+/*
+ * TODO: device.c file uses hardcoded name for watchdog
+	 timer driver "wd_timer2, so we are also using
+	 same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+	.name		= "wd_timer2",
+	.class		= &am33xx_wd_timer_hwmod_class,
+	.main_clk	= "wd_timer1_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.slaves		= am33xx_wd_timer1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_wd_timer1_slaves),
+};
+
+/* wdt0 */
+static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
+	{ .irq = AM33XX_IRQ_WDT0 },
+	{ .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_wdt0_hwmod = {
+	.name		= "wdt0",
+	.class		= &am33xx_wd_timer_hwmod_class,
+	.mpu_irqs	= am33xx_wdt0_irqs,
+	.main_clk	= "wdt0_fck",
+	.clkdm_name	= "l4_wkup_clkdm",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* 'wkup_m3' class */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+	.name		= "wkup_m3",
+};
+
+/* wkup_m3 */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+	.name		= "wkup_m3",
+	.class		= &am33xx_wkup_m3_hwmod_class,
+	.clkdm_name	= "l4_wkup_aon_clkdm",
+	.main_clk	= "wkup_m3_fck",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* L3 SLOW -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+	{
+		.name		= "usbss",
+		.pa_start	= AM33XX_USBSS_BASE,
+		.pa_end		= AM33XX_USBSS_BASE + SZ_4K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.name		= "musb0",
+		.pa_start	= AM33XX_USB0_BASE,
+		.pa_end		= AM33XX_USB0_BASE + SZ_2K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+		.name		= "musb1",
+		.pa_start	= AM33XX_USB1_BASE,
+		.pa_end		= AM33XX_USB1_BASE + SZ_2K - 1,
+		.flags		= ADDR_TYPE_RT
+	},
+	{
+	},
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+	.rev_offs	= 0x0,
+	.sysc_offs	= 0x10,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+	.name		= "usbotg",
+	.sysc		= &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+	{ .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
+	{ .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
+	{ .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
+	{ .irq = -1, },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
+	.master		= &am33xx_l3slow_hwmod,
+	.slave		= &am33xx_usbss_hwmod,
+	.addr		= am33xx_usbss_addr_space,
+	.user		= OCP_USER_MPU,
+	.flags		= OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
+	&am33xx_l3_slow__usbss,
+};
+
+static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
+	{ .role = "clkdcoldo", .clk = "usbotg_fck" },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+	.name		= "usb_otg_hs",
+	.mpu_irqs	= am33xx_usbss_mpu_irqs,
+	.main_clk	= "usbotg_ick",
+	.clkdm_name	= "l4ls_clkdm",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= usbss_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(usbss_opt_clks),
+	.slaves		= am33xx_usbss_slaves,
+	.slaves_cnt	= ARRAY_SIZE(am33xx_usbss_slaves),
+	.class		= &am33xx_usbotg_class,
+};
+
+static __initdata struct omap_hwmod *am33xx_hwmods[] = {
+	/* l3 class */
+	&am33xx_l3_instr_hwmod,
+	&am33xx_l3_main_hwmod,
+	/* l3s class */
+	&am33xx_l3slow_hwmod,
+	/* l4hs class */
+	&am33xx_l4_hs_hwmod,
+	/* l4fw class */
+	&am33xx_l4fw_hwmod,
+	/* l4ls class */
+	&am33xx_l4ls_hwmod,
+	/* l4per class */
+	&am33xx_l4per_hwmod,
+	/* l4wkup class */
+	&am33xx_l4wkup_hwmod,
+
+	/* clkdiv32k class */
+	&am33xx_clkdiv32k_hwmod,
+	/* mpu class */
+	&am33xx_mpu_hwmod,
+	/* adc_tsc class */
+	&am33xx_adc_tsc_hwmod,
+	/* aes class */
+	&am33xx_aes0_hwmod,
+	/* cefuse class */
+	&am33xx_cefuse_hwmod,
+	/* control class */
+	&am33xx_control_hwmod,
+	/* dcan class */
+	&am33xx_dcan0_hwmod,
+	&am33xx_dcan1_hwmod,
+	/* debugss class */
+	&am33xx_debugss_hwmod,
+	/* elm class */
+	&am33xx_elm_hwmod,
+	/* emif_fw class */
+	&am33xx_emif_fw_hwmod,
+	/* epwmss class */
+	&am33xx_epwmss0_hwmod,
+	&am33xx_epwmss1_hwmod,
+	&am33xx_epwmss2_hwmod,
+	/* gpio class */
+	&am33xx_gpio0_hwmod,
+	&am33xx_gpio1_hwmod,
+	&am33xx_gpio2_hwmod,
+	&am33xx_gpio3_hwmod,
+	/* gpmc class */
+	&am33xx_gpmc_hwmod,
+	/* i2c class */
+	&am33xx_i2c1_hwmod,
+	&am33xx_i2c2_hwmod,
+	/* icss class */
+	&am33xx_icss_hwmod,
+	/* ieee5000 class */
+	&am33xx_ieee5000_hwmod,
+	/* mcasp class */
+	&am33xx_mcasp0_hwmod,
+	/* mmc class */
+	&am33xx_mmc0_hwmod,
+	&am33xx_mmc1_hwmod,
+	&am33xx_mmc2_hwmod,
+	/* ocmcram class */
+	&am33xx_ocmcram_hwmod,
+	/* ocpwp class */
+	&am33xx_ocpwp_hwmod,
+	/* rtc class */
+	&am33xx_rtc_hwmod,
+	/* sha0 class */
+	&am33xx_sha0_hwmod,
+	/* smartreflex class */
+	&am33xx_smartreflex0_hwmod,
+	&am33xx_smartreflex1_hwmod,
+	/* spi class */
+	&am33xx_spi0_hwmod,
+	&am33xx_spi1_hwmod,
+	/* spinlock class */
+	&am33xx_spinlock_hwmod,
+	/* uart class */
+	&am33xx_uart1_hwmod,
+	&am33xx_uart2_hwmod,
+	&am33xx_uart3_hwmod,
+	&am33xx_uart4_hwmod,
+	&am33xx_uart5_hwmod,
+	&am33xx_uart6_hwmod,
+	/* timer class */
+	&am33xx_timer0_hwmod,
+	&am33xx_timer1_hwmod,
+	&am33xx_timer2_hwmod,
+	&am33xx_timer3_hwmod,
+	&am33xx_timer4_hwmod,
+	&am33xx_timer5_hwmod,
+	&am33xx_timer6_hwmod,
+	&am33xx_timer7_hwmod,
+	/* wkup_m3 class */
+	&am33xx_wkup_m3_hwmod,
+	/* wd_timer class */
+	&am33xx_wd_timer1_hwmod,
+	/* usbss hwmod */
+	&am33xx_usbss_hwmod,
+	/* cpgmac0 class */
+	&am33xx_cpgmac0_hwmod,
+	&am33xx_wdt0_hwmod, /* Secure WDT */
+	/* tptc class */
+	&am33xx_tptc0_hwmod,
+	&am33xx_tptc1_hwmod,
+	&am33xx_tptc2_hwmod,
+	/* tpcc class */
+	&am33xx_tpcc_hwmod,
+	/* LCDC class */
+	&am33xx_lcdc_hwmod,
+	NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+	return omap_hwmod_register(am33xx_hwmods);
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8b372ed..db2ef2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -612,5 +612,6 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);

 #endif
--
1.7.0.4

[RFC PATCH 09/11] arm:omap:am33xx: Integrate AM33XX hwmods to omap HWMOD framework

[Vaibhav Hiremath]

Hook up AM33XX HWMOD data to OMAP framework.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/Makefile     |    1 +
 arch/arm/mach-omap2/io.c         |    2 ++
 arch/arm/mach-omap2/omap_hwmod.c |   13 +++++++++----
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 19330dc..706a8ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -168,6 +168,7 @@ obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2xxx_ipblock_data.o \
 obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o \
 					   omap_hwmod_2xxx_3xxx_interconnect_data.o \
 					   omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o

 # EMU peripherals
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 82e2817..3afe4e6 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -468,6 +468,8 @@ void __init am33xx_init_early(void)
 	am33xx_voltagedomains_init();
 	am33xx_powerdomains_init();
 	am33xx_clockdomains_init();
+	am33xx_hwmod_init();
+	omap_hwmod_init_postsetup();
 	omap3xxx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6b3088d..dfd3743 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1051,7 +1051,7 @@ static struct omap_hwmod *_lookup(const char *name)
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	if (cpu_is_omap24xx() || (cpu_is_omap34xx() && !cpu_is_am33xx()))
 		return 0;

 	if (!oh->clkdm_name) {
@@ -1134,9 +1134,14 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 	/* XXX check clock enable states */

 	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-		ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-						 oh->prcm.omap2.idlest_reg_id,
-						 oh->prcm.omap2.idlest_idle_bit);
+		if (cpu_is_am33xx())
+			ret = am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
+						oh->prcm.omap4.clkctrl_offs);
+		else
+			ret = omap2_cm_wait_module_ready(
+						oh->prcm.omap2.module_offs,
+						oh->prcm.omap2.idlest_reg_id,
+						oh->prcm.omap2.idlest_idle_bit);
 	} else if (cpu_is_omap44xx()) {
 		if (!oh->clkdm)
 			return -EINVAL;
--
1.7.0.4

[RFC PATCH 10/11] ARM:omap:am33xx: Add clock control api's

[Vaibhav Hiremath]

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
 arch/arm/mach-omap2/Makefile     |    3 +-
 arch/arm/mach-omap2/cminst33xx.c |  311 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cminst33xx.h |   63 ++++++++
 3 files changed, 376 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/cminst33xx.c
 create mode 100644 arch/arm/mach-omap2/cminst33xx.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 706a8ef..784428a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -81,7 +81,8 @@ endif
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 					   vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_OMAPAM33XX)		+= prminst33xx.o cm33xx.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= cminst33xx.o prminst33xx.o cm33xx.o
+
 # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
 # will be removed once the OMAP4 part of the codebase is converted to
 # use OMAP4-specific PRCM functions.
diff --git a/arch/arm/mach-omap2/cminst33xx.c b/arch/arm/mach-omap2/cminst33xx.c
new file mode 100644
index 0000000..e534350
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst33xx.c
@@ -0,0 +1,311 @@
+/*
+ * AM33XX CM instance functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Reference taken from from OMAP4
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm33xx.h"
+#include "cminst33xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm33xx.h"
+
+/*
+ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ *
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+#define CLKCTRL_IDLEST_FUNCTIONAL		0x0
+#define CLKCTRL_IDLEST_INTRANSITION		0x1
+#define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
+#define CLKCTRL_IDLEST_DISABLED			0x3
+
+/* Private functions */
+
+/**
+ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ * bit 0.
+ */
+static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+	u32 v = am33xx_cminst_read_inst_reg(inst, clkctrl_offs);
+	v &= AM33XX_IDLEST_MASK;
+	v >>= AM33XX_IDLEST_SHIFT;
+	return v;
+}
+
+/**
+ * _is_module_ready - can module registers be accessed without causing an abort?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ */
+static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+	u32 v;
+
+	v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
+
+	return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+}
+
+/* Public functions */
+
+/* Read a register in a CM instance */
+u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx)
+{
+	return __raw_readl(cm_base + inst + idx);
+}
+
+/* Write into a register in a CM instance */
+void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx)
+{
+	__raw_writel(val, cm_base + inst + idx);
+}
+
+/* Read-modify-write a register in CM1. Caller must lock */
+u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, idx);
+	v &= ~mask;
+	v |= bits;
+	am33xx_cminst_write_inst_reg(v, inst, idx);
+
+	return v;
+}
+
+u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+	return am33xx_cminst_rmw_inst_reg_bits(bits, bits, inst, idx);
+}
+
+u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+	return am33xx_cminst_rmw_inst_reg_bits(bits, 0x0, inst, idx);
+}
+
+u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, idx);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+/**
+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ * will handle the shift itself.
+ */
+static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, cdoffs);
+	v &= ~AM33XX_CLKTRCTRL_MASK;
+	v |= c << AM33XX_CLKTRCTRL_SHIFT;
+	am33xx_cminst_write_inst_reg(v, inst, cdoffs);
+}
+
+/**
+ * am33xx_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Returns true if the clockdomain referred to by (@inst, @cdoffs)
+ * is in hardware-supervised idle mode, or 0 otherwise.
+ */
+bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, cdoffs);
+	v &= AM33XX_CLKTRCTRL_MASK;
+	v >>= AM33XX_CLKTRCTRL_SHIFT;
+
+	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+}
+
+/**
+ * am33xx_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * hardware-supervised idle mode.  No return value.
+ */
+void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+{
+	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * software-supervised idle mode, i.e., controlled manually by the
+ * Linux OMAP clockdomain code.  No return value.
+ */
+void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+{
+	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cminst_clkdm_force_sleep - try to put a clockdomain into idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into idle
+ * No return value.
+ */
+void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs)
+{
+	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
+}
+
+/**
+ * am33xx_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
+ * waking it up.  No return value.
+ */
+void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+{
+	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
+}
+
+/*
+ *
+ */
+
+/**
+ * am33xx_cminst_wait_module_ready - wait for a module to be in 'func' state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ */
+int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+	int i = 0;
+
+	if (!clkctrl_offs)
+		return 0;
+
+	omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
+			  MAX_MODULE_READY_TIME, i);
+
+	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cminst_wait_module_idle - wait for a module to be in 'disabled'
+ * state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ * like reset assertion or parent clock de-activation must wait the
+ * module to be fully disabled.
+ */
+int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+	int i = 0;
+
+	if (!clkctrl_offs)
+		return 0;
+
+	omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
+			   CLKCTRL_IDLEST_DISABLED),
+			  MAX_MODULE_READY_TIME, i);
+
+	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cminst_module_enable - Enable the modulemode inside CLKCTRL
+ * @mode: Module mode (SW or HW)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
+				u16 clkctrl_offs)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, clkctrl_offs);
+	v &= ~AM33XX_MODULEMODE_MASK;
+	v |= mode << AM33XX_MODULEMODE_SHIFT;
+	am33xx_cminst_write_inst_reg(v, inst, clkctrl_offs);
+}
+
+/**
+ * am33xx_cminst_module_disable - Disable the module inside CLKCTRL
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+			     u16 clkctrl_offs)
+{
+	u32 v;
+
+	v = am33xx_cminst_read_inst_reg(inst, clkctrl_offs);
+	v &= ~AM33XX_MODULEMODE_MASK;
+	am33xx_cminst_write_inst_reg(v, inst, clkctrl_offs);
+}
diff --git a/arch/arm/mach-omap2/cminst33xx.h b/arch/arm/mach-omap2/cminst33xx.h
new file mode 100644
index 0000000..881c0af
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst33xx.h
@@ -0,0 +1,63 @@
+/*
+ * am33xx Clock Management (CM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+#define __ARCH_ASM_MACH_OMAP2_CMINST33XX_H
+
+extern bool am33xx_cminst_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_force_sleep(s16 inst, u16 cdoffs);
+extern void am33xx_cminst_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+
+extern int am33xx_cminst_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+					 u16 clkctrl_offs);
+
+extern void am33xx_cminst_module_enable(u8 mode, u16 inst, s16 cdoffs,
+				       u16 clkctrl_offs);
+extern void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+					u16 clkctrl_offs);
+
+#else
+
+static inline int am33xx_cminst_wait_module_idle(u16 inst, s16 cdoffs,
+					u16 clkctrl_offs)
+{
+	return 0;
+}
+
+static inline void am33xx_cminst_module_enable(u8 mode, u16 inst,
+				s16 cdoffs, u16 clkctrl_offs)
+{
+}
+
+static inline void am33xx_cminst_module_disable(u16 inst, s16 cdoffs,
+				 u16 clkctrl_offs)
+{
+}
+
+#endif
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 am33xx_cminst_read_inst_reg(s16 inst, u16 idx);
+extern void am33xx_cminst_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_cminst_rmw_inst_reg_bits(u32 mask, u32 bits,
+					   s16 inst, s16 idx);
+extern u32 am33xx_cminst_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 am33xx_cminst_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 am33xx_cminst_read_inst_reg_bits(u16 inst, s16 idx, u32 mask);
+
+#endif
--
1.7.0.4

[RFC PATCH 11/11] arm:omap:am33xx: Add am335x support in generic omap_hwmod

[Vaibhav Hiremath]

AM335X is bit different than OMAP3/4 architecture when it comes to
PRCM module, for example, the way module is enabled/disabled.
Although it is closer to OMAP4 architecure but the register offset
and PRCM partitions won't match, so we need to seperate API's
for AM335X.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   29 +++++++++++++++++++++++------
 1 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index dfd3743..4360cb7 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -147,6 +147,7 @@

 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
+#include "cminst33xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
@@ -689,7 +690,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
 static void _enable_module(struct omap_hwmod *oh)
 {
 	/* The module mode does not exist prior OMAP4 */
-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	if (!cpu_is_am33xx() && (cpu_is_omap24xx() || cpu_is_omap34xx()))
 		return;

 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
@@ -698,7 +699,13 @@ static void _enable_module(struct omap_hwmod *oh)
 	pr_debug("omap_hwmod: %s: _enable_module: %d\n",
 		 oh->name, oh->prcm.omap4.modulemode);

-	omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
+	if (cpu_is_am33xx())
+		am33xx_cminst_module_enable(oh->prcm.omap4.modulemode,
+				   oh->clkdm->cm_inst,
+				   oh->clkdm->clkdm_offs,
+				   oh->prcm.omap4.clkctrl_offs);
+	else
+		omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
 				   oh->clkdm->prcm_partition,
 				   oh->clkdm->cm_inst,
 				   oh->clkdm->clkdm_offs,
@@ -715,7 +722,7 @@ static void _enable_module(struct omap_hwmod *oh)
 static void _disable_module(struct omap_hwmod *oh)
 {
 	/* The module mode does not exist prior OMAP4 */
-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	if (!cpu_is_am33xx() && (cpu_is_omap24xx() || cpu_is_omap34xx()))
 		return;

 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
@@ -723,7 +730,12 @@ static void _disable_module(struct omap_hwmod *oh)

 	pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);

-	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+	if (cpu_is_am33xx())
+		am33xx_cminst_module_disable(oh->clkdm->cm_inst,
+				    oh->clkdm->clkdm_offs,
+				    oh->prcm.omap4.clkctrl_offs);
+	else
+		omap4_cminst_module_disable(oh->clkdm->prcm_partition,
 				    oh->clkdm->cm_inst,
 				    oh->clkdm->clkdm_offs,
 				    oh->prcm.omap4.clkctrl_offs);
@@ -1169,7 +1181,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 static int _wait_target_disable(struct omap_hwmod *oh)
 {
 	/* TODO: For now just handle OMAP4+ */
-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	if (!cpu_is_am33xx() && (cpu_is_omap24xx() || cpu_is_omap34xx()))
 		return 0;

 	if (!oh)
@@ -1181,7 +1193,12 @@ static int _wait_target_disable(struct omap_hwmod *oh)
 	if (oh->flags & HWMOD_NO_IDLEST)
 		return 0;

-	return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+	if (cpu_is_am33xx())
+		return am33xx_cminst_wait_module_idle(oh->clkdm->cm_inst,
+					     oh->clkdm->clkdm_offs,
+					     oh->prcm.omap4.clkctrl_offs);
+	else
+		return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
 					     oh->clkdm->cm_inst,
 					     oh->clkdm->clkdm_offs,
 					     oh->prcm.omap4.clkctrl_offs);
--
1.7.0.4

[RFC PATCH 11/11] arm:omap:am33xx: Add am335x support in generic omap_hwmod

[Kevin Hilman]

+Rajendra,

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> AM335X is bit different than OMAP3/4 architecture when it comes to
> PRCM module, for example, the way module is enabled/disabled.
> Although it is closer to OMAP4 architecure but the register offset
> and PRCM partitions won't match, so we need to seperate API's
> for AM335X.
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

Seems like this one can be addressed similarily to the way Rajendra
proposed addressing the powerdomain issue so that OMAP4 code can be
largely reused.

Kevin 

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Kevin Hilman]

Vaibhav Hiremath <hvaibhav@ti.com> writes:

> This patch series adds support for AM335X basic voltage, power,
> clock and HWMOD data to existing OMAP framework.

This series is missing patch 05/11.

Kevin

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hilman, Kevin
> Sent: Thursday, December 01, 2011 7:12 AM
> To: Hiremath, Vaibhav
> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
> arm-kernel at lists.infradead.org; Cousson, Benoit
> Subject: Re: [RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power,
> clock & HWMOD data
> 
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
> 
> > This patch series adds support for AM335X basic voltage, power,
> > clock and HWMOD data to existing OMAP framework.
> 
> This series is missing patch 05/11.
> 
Ohhh...not sure what went bad.

You can access it from, http://arago-project.org/git/people/?p=vaibhav/ti-psp-omap-video.git;a=commit;h=c2754eb60b65c6c574f2d6d871d8846358e40414


I had published the whole series @ Arago.

Thanks,
Vaibhav

> Kevin

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Cousson, Benoit]

On 12/1/2011 1:02 PM, Hiremath, Vaibhav wrote:
>> -----Original Message-----
>> From: Hilman, Kevin
>> Sent: Thursday, December 01, 2011 7:12 AM
>> To: Hiremath, Vaibhav
>> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
>> arm-kernel at lists.infradead.org; Cousson, Benoit
>> Subject: Re: [RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power,
>> clock&  HWMOD data
>>
>> Vaibhav Hiremath<hvaibhav@ti.com>  writes:
>>
>>> This patch series adds support for AM335X basic voltage, power,
>>> clock and HWMOD data to existing OMAP framework.
>>
>> This series is missing patch 05/11.
>>
> Ohhh...not sure what went bad.

This is probably due to the size of the patch. It cannot be > 100k to 
reach the mailing list.

Regards,
Benoit

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Kevin Hilman]

"Hiremath, Vaibhav" <hvaibhav@ti.com> writes:

>> -----Original Message-----
>> From: Hilman, Kevin
>> Sent: Thursday, December 01, 2011 7:12 AM
>> To: Hiremath, Vaibhav
>> Cc: linux-omap at vger.kernel.org; tony at atomide.com; paul at pwsan.com; linux-
>> arm-kernel at lists.infradead.org; Cousson, Benoit
>> Subject: Re: [RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power,
>> clock & HWMOD data
>> 
>> Vaibhav Hiremath <hvaibhav@ti.com> writes:
>> 
>> > This patch series adds support for AM335X basic voltage, power,
>> > clock and HWMOD data to existing OMAP framework.
>> 
>> This series is missing patch 05/11.
>> 
> Ohhh...not sure what went bad.
>
> You can access it from, http://arago-project.org/git/people/?p=vaibhav/ti-psp-omap-video.git;a=commit;h=c2754eb60b65c6c574f2d6d871d8846358e40414
>
>
> I had published the whole series @ Arago.
>

OK, but using Arago, I will also get a bunch of other out of tree code.

Can you create a branch for base am33x support against a recent mainline
(like v3.2-rc3) for easier review/testing of just the AM33x support?

Kevin

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Kevin Hilman]

On 12/01/2011 06:58 AM, Kevin Hilman wrote:
> Can you create a branch for base am33x support against a recent mainline
> (like v3.2-rc3) for easier review/testing of just the AM33x support?

Nevermind, I now see your am335x-staging branch in the Arago tree you
mentioned.

Thanks,

Kevin

[RFC PATCH 00/11] arm:omap:am33xx: Add basic voltage, power, clock & HWMOD data

[Tony Lindgren]

* Vaibhav Hiremath <hvaibhav@ti.com> [111120 08:44]:
> 
>  34 files changed, 7525 insertions(+), 15 deletions(-)

Clearly we can't merge this amount of static SoC specific
hwmod/mux data after the all that's been discussed over
this year.

We just have to have a better way of doing this.

For now, we already have the SoC specific init functions
available, so I suggest taking a hard look how to dynamically
allocate these data structures and populate them with the
SoC specific init functions.

Then later on we may be able to pass some of the data such
as module base addresses from device tree. But I'm guessing
that the SoC specific inits should already squeeze this down
into something tolerable.

Regards,

Tony