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Wed, 22 Dec 2021 18:07:44 +0000 Date: Wed, 22 Dec 2021 18:07:44 +0000 Message-ID: <874k701pjj.wl-maz@kernel.org> From: Marc Zyngier To: Felix Fietkau Cc: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Olof Johansson , soc@kernel.org, Rob Herring , john@phrozen.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523 In-Reply-To: References: <20211220211854.89452-1-nbd@nbd.name> <20211220211854.89452-4-nbd@nbd.name> <04137b5dd876899af0da15f7dbc159fc@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 91.161.240.24 X-SA-Exim-Rcpt-To: nbd@nbd.name, linux-arm-kernel@lists.infradead.org, arnd@arndb.de, olof@lixom.net, soc@kernel.org, robh+dt@kernel.org, john@phrozen.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211222_100748_126672_EF4187C3 X-CRM114-Status: GOOD ( 29.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 22 Dec 2021 16:04:07 +0000, Felix Fietkau wrote: > > > On 2021-12-21 16:02, Marc Zyngier wrote: > > On 2021-12-20 21:18, Felix Fietkau wrote: > >> From: John Crispin > >> > >> Add basic support for Airoha EN7523, enough for booting to console. > >> > >> The UART is basically 8250-compatible, except for the clock selection. > >> A clock-frequency value is synthesized to get this to run at 115200 > >> bps. > >> > >> Signed-off-by: John Crispin > >> Signed-off-by: Bert Vermeulen > >> Signed-off-by: Felix Fietkau > >> --- > >> arch/arm/boot/dts/Makefile | 2 + > >> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++ > >> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++ > >> 3 files changed, 143 insertions(+) > >> create mode 100644 arch/arm/boot/dts/en7523-evb.dts > >> create mode 100644 arch/arm/boot/dts/en7523.dtsi > >> > > > > [...] > > > >> + gic: interrupt-controller@9000000 { > >> + compatible = "arm,gic-v3"; > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>; > > > > You are missing the 3 extra regions implemented by the A53 cores > > (GICC, GICV, GICH). Please see the binding and the A53 TRM. > The SoC memory map documentation contains an address for GICC, but not > for the other two. Maybe this CPU doesn't implement them. Please read the CPU TRM (it is publicly available from the ARM web site). GICC, GICV and GICH are all at a fixed offset form each other, and are always implemented by the A53 when connected to a GICv3. > I will add GICC in v9 Please add all 3 missing regions. > > >> + interrupts = ; > >> + }; > >> + > >> + timer { > >> + compatible = "arm,armv7-timer"; > > > > This is an ARMv8 CPU, even when used in 32bit mode. > > > >> + interrupt-parent = <&gic>; > >> + interrupts = , > >> + , > >> + , > >> + ; > >> + clock-frequency = <25000000>; > > > > Why isn't this properly configured by the firmware? > I don't know. Then drop it. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel