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Tue, 10 Aug 2021 13:15:16 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mDRaz-003u5c-BF for linux-arm-kernel@lists.infradead.org; Tue, 10 Aug 2021 13:15:07 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0B18E60F38; Tue, 10 Aug 2021 13:15:05 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mDRaw-0043sk-Qn; Tue, 10 Aug 2021 14:15:03 +0100 Date: Tue, 10 Aug 2021 14:15:02 +0100 Message-ID: <874kbxbfvt.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Lezcano , Thomas Gleixner , Peter Shier , Raghavendra Rao Ananta , Ricardo Koller , Oliver Upton , Will Deacon , Catalin Marinas , Linus Walleij , kernel-team@android.com Subject: Re: [PATCH 08/13] clocksource/arm_arch_timer: Work around broken CVAL implementations In-Reply-To: <20210810123407.GB52842@C02TD0UTHF1T.local> References: <20210809152651.2297337-1-maz@kernel.org> <20210809152651.2297337-9-maz@kernel.org> <20210810123407.GB52842@C02TD0UTHF1T.local> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, pshier@google.com, rananta@google.com, ricarkol@google.com, oupton@google.com, will@kernel.org, catalin.marinas@arm.com, linus.walleij@linaro.org, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210810_061505_492909_03A2CE08 X-CRM114-Status: GOOD ( 40.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 10 Aug 2021 13:34:07 +0100, Mark Rutland wrote: > > On Mon, Aug 09, 2021 at 04:26:46PM +0100, Marc Zyngier wrote: > > The Applied Micro XGene-1 SoC has a busted implementation of the > > CVAL register: it looks like it is based on TVAL instead of the > > other way around. The net effect of this implementation blunder > > is that the maximum deadline you can program in the timer is > > 32bit wide. > > > > Detect the problematic case and limit the timer to 32bit deltas. > > Note that we don't tie this bug to XGene specifically, as it may > > also catch similar defects on other high-quality implementations. > > Do we know of any other implementations that have a similar bug? > > > Signed-off-by: Marc Zyngier > > --- > > drivers/clocksource/arm_arch_timer.c | 38 +++++++++++++++++++++++++++- > > 1 file changed, 37 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > > index 895844c33351..1c596cd3cc5c 100644 > > --- a/drivers/clocksource/arm_arch_timer.c > > +++ b/drivers/clocksource/arm_arch_timer.c > > @@ -778,9 +778,42 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt, > > return 0; > > } > > > > +static u64 __arch_timer_check_delta(void) > > +{ > > +#ifdef CONFIG_ARM64 > > + u64 tmp; > > + > > + /* > > + * XGene-1 implements CVAL in terms of TVAL, meaning that the > > + * maximum timer range is 32bit. Shame on them. Detect the > > + * issue by setting a timer to now+(1<<32), which will > > + * immediately fire on the duff CPU. > > + */ > > + write_sysreg(0, cntv_ctl_el0); > > + isb(); > > + tmp = read_sysreg(cntvct_el0) | BIT(32); > > + write_sysreg(tmp, cntv_cval_el0); > > This will fire on legitimate implementations fairly often. Consider if > we enter this function at a time where CNTCVT_EL0[32] == 1, where: > > * At 100MHz, bit 32 flips every ~42.95 > * At 200MHz, bit 32 flips every ~21.47 > * At 1GHz, bit 32 flips every ~4.29s > > ... and ThunderX2 has a 200MHz frequency today, with SBSA recommending > 100MHz. Yup, you're right, this is silly. Orr-ing the bit is a bad enough bug (it really should be a +), but also preemption in a guest will add another set of false positives. > What does XGene-1 return upon a read of CVAL? If it always returns 0 for > the high bits, we could do a timing-insensitive check for truncation of > CVAL, e.g. > > | /* CVAL must be at least 56 bits wide, as with CNT */ > | u64 mask = GENMASK(55, 0); > | u64 val; > | > | write_sysreg(mask, cntv_cval_el0); > | val = read_sysread(cnt_cval_el0); > | > | if (val != mask) { > | /* What a great CPU */ > | } No, the register itself returns what has been written. But only the low 32bits of the delta trickle into TVAL on write, which is then used as a countdown. I guess I could play the same trick as above with a higher bit, but it still is pretty unreliable, as it could then wrap through 0. Maybe I'll just check the MIDR in the end... M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel