From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Baruch Siach <baruch@tkos.co.il>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Baruch Siach <baruch@tkos.co.il>, Denis Odintsov <oversun@me.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
Date: Tue, 19 Feb 2019 16:13:33 +0100 [thread overview]
Message-ID: <874l8z3j6q.fsf@FE-laptop> (raw)
In-Reply-To: <611c942e1da6404d47cf3ff4a6bd33d7bdab4e13.1550427700.git.baruch@tkos.co.il>
Hi Baruch,
On dim., févr. 17 2019, Baruch Siach <baruch@tkos.co.il> wrote:
> The PHY reset signal goes to mpp43 on CP0.
>
Applied on mvebu/fixes with the Fixes tag pointed by Andrew.
Thanks,
Gregory
> Reported-by: Denis Odintsov <oversun@me.com>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index 5b4a9609e31f..2468762283a5 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -351,7 +351,7 @@
> reg = <0>;
> pinctrl-names = "default";
> pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> - reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
> + reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> };
>
> --
> 2.20.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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prev parent reply other threads:[~2019-02-19 15:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-17 18:21 [PATCH] arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal Baruch Siach
2019-02-17 18:26 ` Andrew Lunn
2019-02-19 15:13 ` Gregory CLEMENT [this message]
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