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From: Thomas Gleixner <tglx@linutronix.de>
To: Michael Kelley <mhklinux@outlook.com>,
	Steven Price <steven.price@arm.com>,
	Marc Zyngier <maz@kernel.org>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Will Deacon <will@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: RE: [PATCH 1/2] irqchip/gic-v3-its: Share ITS tables with a non-trusted hypervisor
Date: Wed, 02 Oct 2024 15:43:13 +0200	[thread overview]
Message-ID: <875xqay61a.ffs@tglx> (raw)
In-Reply-To: <SN6PR02MB41579C5C46B4F5F72A888743D4992@SN6PR02MB4157.namprd02.prod.outlook.com>

On Mon, Sep 09 2024 at 03:47, Michael Kelley wrote:
>> +	ret = set_memory_decrypted((unsigned long)page_address(page),
>> +				   1 << order);
>> +	if (WARN_ON(ret))
>
> On the x86 side, the WARN is done in the implementation of
> set_memory_decrypted()/encrypted() so that each call site doesn't
> need to do the WARN. Each call site must only leak the memory
> if the return value indicates other than success. There are call sites
> in architecture neutral code (such as for swiotlb and DMA direct)
> that expect the WARN is in set_memory_decrypted()/encrypted().
> To recap a previous discussion, we want the WARN for notification,
> but also so the most security-conscious users can set
> kernel.panic_on_warn=1 to stop further processing if there are
> problems in the decryption/encryption operation.

What's the resolution of this?

Thanks,

        tglx


  reply	other threads:[~2024-10-02 13:44 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-05  9:17 [PATCH 0/2] irqchip/gic-v3-its: Mark ITS tables as decrypted Steven Price
2024-09-05  9:17 ` [PATCH 1/2] irqchip/gic-v3-its: Share ITS tables with a non-trusted hypervisor Steven Price
2024-09-06 16:36   ` Catalin Marinas
2024-09-09  3:47   ` Michael Kelley
2024-10-02 13:43     ` Thomas Gleixner [this message]
2024-10-02 13:59       ` Steven Price
2024-09-05  9:17 ` [PATCH 2/2] irqchip/gic-v3-its: Rely on genpool alignment Steven Price
2024-09-06 16:46   ` Catalin Marinas

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