From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Marc Zyngier <maz@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@bootlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH 1/4] irqchip/riscv-imsic: Handle non-atomic MSI updates for device
Date: Thu, 12 Dec 2024 20:51:13 +0100 [thread overview]
Message-ID: <877c84ade6.ffs@tglx> (raw)
In-Reply-To: <CAK9=C2XEhtB00y6WTMaO0X=7K820T_BSCLA5bw6hJbfvQAD+Pw@mail.gmail.com>
On Thu, Dec 12 2024 at 22:11, Anup Patel wrote:
>> --- a/kernel/irq/chip.c
>> +++ b/kernel/irq/chip.c
>> @@ -47,6 +47,13 @@ int irq_set_chip(unsigned int irq, const
>> return -EINVAL;
>>
>> desc->irq_data.chip = (struct irq_chip *)(chip ?: &no_irq_chip);
>> +
>> + if (IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS) && chip) {
>> + if (chip->flags & IRQCHIP_MOVE_DEFERRED)
>> + irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT);
>> + else
>> + irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
>> + }
>
> We need similar changes in irq_domain_set_hwirq_and_chip()
> because we use IRQ_DOMAIN_HIERARCHY in RISC-V.
Grr, you are right. Let me add that to the base patch.
>> irq_put_desc_unlock(desc, flags);
>> /*
>> * For !CONFIG_SPARSE_IRQ make the irq show up in
>> @@ -1114,16 +1121,21 @@ void irq_modify_status(unsigned int irq,
>> trigger = irqd_get_trigger_type(&desc->irq_data);
>>
>> irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
>> - IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
>> + IRQD_TRIGGER_MASK | IRQD_LEVEL);
>> if (irq_settings_has_no_balance_set(desc))
>> irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
>> if (irq_settings_is_per_cpu(desc))
>> irqd_set(&desc->irq_data, IRQD_PER_CPU);
>> - if (irq_settings_can_move_pcntxt(desc))
>> - irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
>> if (irq_settings_is_level(desc))
>> irqd_set(&desc->irq_data, IRQD_LEVEL);
>>
>> + /* Keep this around until x86 is converted over */
>> + if (!IS_ENABLED(CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS)) {
>> + irqd_clear(&desc->irq_data, IRQD_MOVE_PCNTXT);
>> + if (irq_settings_can_move_pcntxt(desc))
>> + irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
>> + }
>> +
>
> These changes in irq_modify_status() need to be dropped to support
> the above changes in irq_domain_set_hwirq_and_chip().
Why? With CONFIG_GENERIC_PENDING_IRQ_CHIPFLAGS enabled this hunk is
compiled out. So nothing is modifying PCNTXT here. That's the whole
point.
Thanks,
tglx
next prev parent reply other threads:[~2024-12-12 19:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-08 15:07 [PATCH 0/4] Move RISC-V IMSIC driver to the common MSI lib Anup Patel
2024-12-08 15:07 ` [PATCH 1/4] irqchip/riscv-imsic: Handle non-atomic MSI updates for device Anup Patel
2024-12-08 20:14 ` Thomas Gleixner
2024-12-09 12:08 ` Anup Patel
2024-12-09 15:53 ` Thomas Gleixner
2024-12-09 17:09 ` Anup Patel
2024-12-12 16:41 ` Anup Patel
2024-12-12 19:51 ` Thomas Gleixner [this message]
2024-12-13 15:43 ` Anup Patel
2024-12-08 15:07 ` [PATCH 2/4] irqchip/irq-msi-lib: Optionally set default irq_eoi/irq_ack Anup Patel
2024-12-08 15:07 ` [PATCH 3/4] irqchip/riscv-imsic: Set irq_set_affinity for IMSIC base Anup Patel
2024-12-08 15:07 ` [PATCH 4/4] irqchip/riscv-imsic: Move to common MSI lib Anup Patel
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