From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 064EFC77B7A for ; Tue, 16 May 2023 14:21:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qX6j7WWQeOTA1+27FnhiTNKKSA5eer/otZuSq+En5eM=; b=g5wWR4lZdd9V96 pFG+pVLXSl9gIsCctM8KuoPbkpYUkzFjjf3xzvqhX1jxwiJB3A2dGNdHAVcK5+amsG7IHNamhLFX+ V84t3IXx8Y4CFSTg0T7XRgJ77sl45Z894tz3wxPsiqgubCKPKdZVOi38NGQS9Hlhm6VJu+zTEVXA5 WDblyKnXiNxdoT6DCt9iNLK6HpjZEM0qKcCdYu7J7V9u2bGsVuWR2hFFBxs9u3jn7oEx2LTrQ4SlN i1lPye6lrjiWaD/Moc7BCpIShkVGdsD1IXR36zE7doQqnnrSmIPkTCnkZXK2BPxuX3Ubays1PaQix xlsw9jxQjufR/zZ2JVwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pyvYS-0064GK-0U; Tue, 16 May 2023 14:21:32 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pyvYP-0064FO-0b for linux-arm-kernel@lists.infradead.org; Tue, 16 May 2023 14:21:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1684246887; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=iI7IGPaVhBWiA9o2JZBNiM8ifHsTLnjxJmTcjx0w6Sw=; b=QtQ/3mqgyw9/LMYeAXvecsP7l35OXUFBk8gfXSUqKopMUSXw0Ua3kJhqW/gjMiaphwgpZR YR+GRITTgVdyrPl4L038eCVVZs/CDtToqAVKJdHmCyIB1M8Mk9d4evsC/srfmIR6bMHXNA ymTorliik4os2ImjLJKPBAsr0v/9N4w= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-651-xYJHXN4xNuSjXGgPbW4jhw-1; Tue, 16 May 2023 10:21:24 -0400 X-MC-Unique: xYJHXN4xNuSjXGgPbW4jhw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E775C85C06E; Tue, 16 May 2023 14:21:23 +0000 (UTC) Received: from localhost (dhcp-192-239.str.redhat.com [10.33.192.239]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9FB852166B31; Tue, 16 May 2023 14:21:23 +0000 (UTC) From: Cornelia Huck To: Shameerali Kolothum Thodi , Marc Zyngier Cc: Jing Zhang , KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: RE: [PATCH v8 0/6] Support writable CPU ID registers from userspace In-Reply-To: Organization: Red Hat GmbH References: <20230503171618.2020461-1-jingzhangos@google.com> <2ef9208dabe44f5db445a1061a0d5918@huawei.com> <868rdomtfo.wl-maz@kernel.org> <1a96a72e87684e2fb3f8c77e32516d04@huawei.com> <87cz30h4nx.fsf@redhat.com> <867ct8mnel.wl-maz@kernel.org> User-Agent: Notmuch/0.37 (https://notmuchmail.org) Date: Tue, 16 May 2023 16:21:22 +0200 Message-ID: <877ct8gxwd.fsf@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230516_072129_300269_49267773 X-CRM114-Status: GOOD ( 24.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 16 2023, Shameerali Kolothum Thodi wrote: >> -----Original Message----- >> From: Marc Zyngier [mailto:maz@kernel.org] >> Sent: 16 May 2023 14:12 >> To: Cornelia Huck >> Cc: Shameerali Kolothum Thodi ; >> Jing Zhang ; KVM ; >> KVMARM ; ARMLinux >> ; Oliver Upton ; >> Will Deacon ; Paolo Bonzini ; >> James Morse ; Alexandru Elisei >> ; Suzuki K Poulose ; >> Fuad Tabba ; Reiji Watanabe ; >> Raghavendra Rao Ananta >> Subject: Re: [PATCH v8 0/6] Support writable CPU ID registers from >> userspace >> >> On Tue, 16 May 2023 12:55:14 +0100, >> Cornelia Huck wrote: >> > >> > Do you have more concrete ideas for QEMU CPU models already? Asking >> > because I wanted to talk about this at KVM Forum, so collecting what >> > others would like to do seems like a good idea :) >> >> I'm not being asked, but I'll share my thoughts anyway! ;-) >> >> I don't think CPU models are necessarily the most important thing. >> Specially when you look at the diversity of the ecosystem (and even >> the same CPU can be configured in different ways at integration >> time). Case in point, Neoverse N1 which can have its I/D caches made >> coherent or not. And the guest really wants to know which one it is >> (you can only lie in one direction). >> >> But being able to control the feature set exposed to the guest from >> userspace is a huge benefit in terms of migration. > > Yes, this is what we also need and was thinking of adding a named CPU with > common min feature set exposed to Guest. There were some previous > attempts to add the basic support in Qemu here, > > https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg00087.html Thanks for the link. > >> Now, this is only half of the problem (and we're back to the CPU >> model): most of these CPUs have various degrees of brokenness. Most of >> the workarounds have to be implemented by the guest, and are keyed on >> the MIDR values. So somehow, you need to be able to expose *all* the >> possible MIDR values that a guest can observe in its lifetime. > > Ok. This will be a problem and I am not sure this has an impact on our > platforms or not. Oh, I see that the MIDR fun had already been mentioned in a reply to the first version of that patchset; this needs to be addressed for the general case, I guess... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel