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Mon, 07 Mar 2022 14:39:25 +0000 Date: Mon, 07 Mar 2022 14:39:25 +0000 Message-ID: <877d9525eq.wl-maz@kernel.org> From: Marc Zyngier To: , , Linu Cherian Cc: , , , Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR In-Reply-To: <20220307143014.22758-1-lcherian@marvell.com> References: <20220307143014.22758-1-lcherian@marvell.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: catalin.marinas@arm.com, will@kernel.org, lcherian@marvell.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuc.decode@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220307_063930_719531_BDC1DF48 X-CRM114-Status: GOOD ( 23.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 07 Mar 2022 14:30:14 +0000, Linu Cherian wrote: > > When a IAR register read races with a GIC interrupt RELEASE event, > GIC-CPU interface could wrongly return a valid INTID to the CPU > for an interrupt that is already released(non activated) instead of 0x3ff. > > As a side effect, an interrupt handler could run twice, once with > interrupt priority and then with idle priority. > > As a workaround, gic_read_iar is updated so that it will return a > valid interrupt ID only if there is a change in the active priority list > after the IAR read on all the affected Silicons. > > Since there are silicon variants where both 23154 and 38545 are applicable, > workaround for erratum 23154 has been extended to address both of them. > > Signed-off-by: Linu Cherian > --- > Changes since V2: > - Changed masked part number to individual part numbers > - Added additional comment to clarify on priority groups > > > Changes since V1: > - IIDR based quirk management done for 23154 has been reverted > - Extended existing 23154 errata to address 38545 as well, > so that existing static keys are reused. > - Added MIDR based support macros to cover all the affected parts > - Changed the unlikely construct to likely construct in the workaround > function. > > > > > Documentation/arm64/silicon-errata.rst | 2 +- > arch/arm64/Kconfig | 8 ++++++-- > arch/arm64/include/asm/arch_gicv3.h | 23 +++++++++++++++++++++-- > arch/arm64/include/asm/cputype.h | 13 +++++++++++++ > arch/arm64/kernel/cpu_errata.c | 20 +++++++++++++++++--- > 5 files changed, 58 insertions(+), 8 deletions(-) Looks good to me this time. Catalin, Will: happy to take this into the irqchip tree for 5.18 with your Ack, or you can take it into the arm64 tree with my Reviewed-by: Marc Zyngier Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel