From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA260CDB466 for ; Sat, 20 Jun 2026 08:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Subject:Cc:To:From: Message-ID:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pChRParA4h9txJxRD2Y/ykZeyn6BMFeYT/V2eKH1xSU=; b=JygdbdcHf9+NBw0Sdo12c2kVEg 2qGGSEytRtakeswzwAqa+pmIIjaNmNM0BJUuMvr7g41DnhUfn2BNEDyVSsiHOKHbq1AvQ+ngBUTD2 QIjLEHnLDt9qnhrh8IVJo4U8dMhMoKuBgviV1nkPrnRwgmC+WwzUvmqH01RvvJSKMPYNkKOwK1ar8 cyeabbRZWYbJdzeTLakzcSgvGdxK6cC6JxkD6oKHHjGp7EVlWQwplEwUc2XzqjaXaTXU9YXVdRTjk PyHBVdq3FY7FEQICnXPKzukyIDndsJMdHodvtbvoR9Vurre/CaMQ8bdyMZHOVXYLvaHWzpV1x3cab EOGEogxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1warN6-00000003HEN-0nYE; Sat, 20 Jun 2026 08:48:12 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1warN4-00000003HE1-0cLP; Sat, 20 Jun 2026 08:48:10 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 8F86144107; Sat, 20 Jun 2026 08:48:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6FFFC1F00A3A; Sat, 20 Jun 2026 08:48:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781945289; bh=pChRParA4h9txJxRD2Y/ykZeyn6BMFeYT/V2eKH1xSU=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=H5KtmN+ijbdyuzPesz3it5iE+TRcUsm8EBBF0YPuy3T6a3ZYfxIJmmzWNTF5RWMoH /nDLQpsr0zo18vFJbeY21BNv2HrZrRscDd8OQKzHUZMW48the48nmBkBYiCn2LDNzJ cUfNJen6wZn1R5f3CAZ20ImCxZYEJUq8oPTp8yv55fhr++qQGkaexAH8xXUjIgjG0U OII6ilcjRhHIB3/EdjD0s4tSHEOObaLoYTiVSgjsNQtr8TNlBDCokBwq4HItemnFYH WlV7rO9ryBU5aRXVgKZdPa7EFg7szpqqvpGn5rL+GczMb1D9yxNlyGF842RJiERJHY dz6G0Q3XSOp2Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1warN1-0000000EUQb-1aCO; Sat, 20 Jun 2026 08:48:07 +0000 Date: Sat, 20 Jun 2026 09:49:14 +0100 Message-ID: <878q898ulx.wl-maz@kernel.org> From: Marc Zyngier To: Daniel Drake Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com, andrea.porta@suse.com Subject: Re: [PATCH] arm64: dts: broadcom: bcm2712: Remove non-functional EL2 virtual timer In-Reply-To: <20260619204832.586079-1-dan@reactivated.net> References: <20260619204832.586079-1-dan@reactivated.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: dan@reactivated.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com, andrea.porta@suse.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Daniel, Thanks for posting this. On Fri, 19 Jun 2026 21:48:32 +0100, Daniel Drake wrote: >=20 > Commit d87773de9efe1 ("clocksource/drivers/arm_arch_timer: Default to > EL2 virtual timer when running VHE") causes boot to hang on > Raspberry Pi 5. The newly-selected EL2 virtual timer does not generate > any interrupts, even though the GIC_DIST_ENABLE_SET flag has been > confirmed set via readback. >=20 > The reasons for this failure are unknown, however it is likely that > this timer was never tested. Raspberry Pi's original devicetree did The timer is part of the CPU, and there are enough A76 implementations around to prove that it actually works. The same can be said for the GIC400 this is (supposedly) attached to. > not include this timer interrupt; it was only introduced via a > suggestion[1] made in code review as part of the upstreaming process. > (Current RPi firmware versions do include this timer, but only because > they rebased on top of the upstreamed devicetree starting with > Linux 6.12) >=20 > Until more is known about this non-firing timer interrupt, remove > the devicetree entry to enable RPi5 devices to boot. I'd like to understand the reason why the timer interrupt isn't being delivered *before* we paper over it, and not the other way around. Each of the CPUs definitely have an EL2 virtual timer, the GIC has a per-CPU interrupt, but somehow the two don't seem to be linked. Since DT is supposed to describe the HW, I'd expect someone from Broadcom or RPi to shine a light on this issue. Integration mistakes happen, and we work around them (see the handful of Samsung SoCs where the timer interrupt was simply not wired). But we absolutely need to know what we are dealing with beforehand. Finally, just hacking the DT is not enough. Assuming that the timer is indeed unusable, we need to cope with the fact that there are DTs describing it in the wild, as nobody should be forced to upgrade their DT in lockstep with the kernel. For that, you'd also need something like the patch below (untested, and in need of a proper commit message, which I expect the SoC vendor to provide). Thanks, M. =46rom 9de354b472e28112d73fdb63be986f68fb3c91a9 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 20 Jun 2026 09:32:09 +0100 Subject: [PATCH] clocksource/drivers/arm_arch_timer: Workaround RPi5 broken EL2 virtual timer Insert $REASON here. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 4adf756423de9..de9007a30a923 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1090,6 +1090,16 @@ static int __init arch_timer_common_init(void) return arch_timer_arch_init(); } =20 +static bool __init has_broken_el2_vtimer(void) +{ + static const char * const broken_el2_vtimer[] __initconst =3D { + "brcm,bcm2712", + NULL + }; + + return of_machine_compatible_match(broken_el2_vtimer); +} + /** * arch_timer_select_ppi() - Select suitable PPI for the current system. * @@ -1115,7 +1125,8 @@ static int __init arch_timer_common_init(void) static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void) { if (is_kernel_in_hyp_mode()) { - if (arch_timer_ppi[ARCH_TIMER_HYP_VIRT_PPI]) + if (arch_timer_ppi[ARCH_TIMER_HYP_VIRT_PPI] && + !has_broken_el2_vtimer()) return ARCH_TIMER_HYP_VIRT_PPI; =20 pr_warn_once(FW_BUG "VHE-capable CPU without EL2 virtual timer interrupt= \n"); --=20 2.47.3 --=20 Jazz isn't dead. It just smells funny.