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b=ZHLEilRK1/fpHx8hG0gRA5X17AKl/beVrxp0dZAR1a4UVRkjwA9ENlXMPbISOGUZW wu7UvLFHz7eMYuIIoitXKsn4AmPNO+AOzE0XuDAqUMiXOEVJzRae3ZjoIR9X7mhEbW 1la48yhq7xByXn31y1wyk5BV62W84SgRAunxfB5046PdGsv+jdSUt5+pfdJJrvknB7 QnXDlQIku/qaSRX84l+UhkBPOn4Xooef4qzjAC6mQVx9KHw/uvfgU9LEys48k1zjUe sm6FO4Afu01VRp9yRc7tg17hAv5ZKCpmuLkdciMqf1L9Z6cBDz08czvLGhcRowW92a 6YD1xgZGZrhXw== Received: from ip-185-104-136-29.ptr.icomera.net ([185.104.136.29] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qYLSy-006wSt-Cu; Tue, 22 Aug 2023 08:06:16 +0100 Date: Tue, 22 Aug 2023 08:06:03 +0100 Message-ID: <878ra3pndw.wl-maz@kernel.org> From: Marc Zyngier To: Jing Zhang Cc: KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang Subject: Re: [PATCH v9 05/11] KVM: arm64: Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 In-Reply-To: <20230821212243.491660-6-jingzhangos@google.com> References: <20230821212243.491660-1-jingzhangos@google.com> <20230821212243.491660-6-jingzhangos@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.104.136.29 X-SA-Exim-Rcpt-To: jingzhangos@google.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, pbonzini@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, tabba@google.com, reijiw@google.com, rananta@google.com, surajjs@amazon.com, cohuck@redhat.com, shahuang@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_000622_413216_3535AEE0 X-CRM114-Status: GOOD ( 25.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 21 Aug 2023 22:22:37 +0100, Jing Zhang wrote: > > All valid fields in ID_AA64DFR0_EL1 and ID_DFR0_EL1 are writable > from userspace with this change. > RES0 fields and those fields hidden by KVM are not writable. > > Signed-off-by: Jing Zhang > --- > arch/arm64/kvm/sys_regs.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index afade7186675..20fc38bad4e8 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1931,6 +1931,8 @@ static bool access_spsr(struct kvm_vcpu *vcpu, > return true; > } > > +#define ID_AA64DFR0_EL1_RES0_MASK (GENMASK(59, 56) | GENMASK(27, 24) | GENMASK(19, 16)) > + > /* > * Architected system registers. > * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 > @@ -2006,7 +2008,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > .set_user = set_id_dfr0_el1, > .visibility = aa32_id_visibility, > .reset = read_sanitised_id_dfr0_el1, > - .val = ID_DFR0_EL1_PerfMon_MASK, }, > + .val = GENMASK(31, 0), }, Can you *please* look at the register and realise that we *don't* support writing to the whole of the low 32 bits? What does it mean to allow selecting the M-profile debug? Or the memory-mapped trace? You are advertising a lot of crap to userspace, and that's definitely not on. > ID_HIDDEN(ID_AFR0_EL1), > AA32_ID_SANITISED(ID_MMFR0_EL1), > AA32_ID_SANITISED(ID_MMFR1_EL1), > @@ -2055,7 +2057,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > .get_user = get_id_reg, > .set_user = set_id_aa64dfr0_el1, > .reset = read_sanitised_id_aa64dfr0_el1, > - .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, > + .val = ~(ID_AA64DFR0_EL1_PMSVer_MASK | ID_AA64DFR0_EL1_RES0_MASK), }, And it is the same thing here. Where is the handling code to deal with variable breakpoint numbers? Oh wait, there is none. Really, the only thing we support writing to are the PMU and Debug versions. And nothing else. What does it mean for userspace? Either the write will be denied despite being advertised a writable field (remember the first patch of the series???), or we'll blindly accept the write and further ignore the requested values. Do you really think any of this is acceptable? This is the *9th* version of this series, and we're still battling over some extremely basic userspace issues... I don't think we can merge this series as is stands. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel