From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E78A5C388F9 for ; Thu, 19 Nov 2020 06:23:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7131621D91 for ; Thu, 19 Nov 2020 06:23:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="TSzjHIlI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7131621D91 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7/el2BB80th957Qv/6sDG93h1tSbF13SSyTxM44IukU=; b=TSzjHIlITLlkiKIziEFHrAget XLodPXh9BkIWZT/kLfc3sh2W9FluypRK9W8WmIiR2EziYD6xWes7khnV09Kvsk2Y0LNPuQUSsVJ8U fmjOYaiIpQ92WAKd+lrxyrn8C1ndXbit6fKUNAvGHBQFPa/s1nV0jAFHwKFqKy+9vZLalS/dD4hZw 3h9gHbmWaZPXi/CXGsbCnzebeEkZ8XbAWR+siUrUIHI8vS0xjLesfRYYO9kcYnkc7JA0msCeDSifd PlEAIqvsERkpdgFo6fgvh3c0EmVpXDwaiZ0BccLzizWqbc/ernPHQYTjomRKF6T9sqHCpk+xNUSlo vaDxLx24g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfdKM-000123-Ae; Thu, 19 Nov 2020 06:21:54 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfdKI-00011P-NZ for linux-arm-kernel@lists.infradead.org; Thu, 19 Nov 2020 06:21:52 +0000 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 9466B44064A; Thu, 19 Nov 2020 08:21:48 +0200 (IST) References: <20201118231811.GH1853236@lunn.ch> User-agent: mu4e 1.4.13; emacs 26.3 From: Baruch Siach To: Andrew Lunn Subject: Re: [PATCH 3/5] gpio: mvebu: add pwm support for Armada 8K/7K In-reply-to: <20201118231811.GH1853236@lunn.ch> Date: Thu, 19 Nov 2020 08:21:48 +0200 Message-ID: <878sax6f43.fsf@tarshish> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_012151_406813_3895D537 X-CRM114-Status: GOOD ( 31.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, Sascha Hauer , Jason Cooper , linux-gpio@vger.kernel.org, Linus Walleij , Chris Packham , Bartosz Golaszewski , Thierry Reding , Thomas Petazzoni , Uwe =?utf-8?Q?Kleine-K?= =?utf-8?Q?=C3=B6nig?= , Ralph Sennhauser , Lee Jones , Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andrew, On Thu, Nov 19 2020, Andrew Lunn wrote: > On Wed, Nov 18, 2020 at 12:30:44PM +0200, Baruch Siach wrote: >> Use the pwm-offset DT property to store the location of PWM signal >> duration registers. >> >> Since we have more than two GPIO chips per system, we can't use the >> alias id to differentiate between them. Use the offset value for that. >> >> Move mvebu_pwm_probe() call before irq support code. The AP80x does not >> provide irq support, but does provide PWM. Don't skip PWM probe because >> of that. >> >> Signed-off-by: Baruch Siach [snip] >> @@ -781,51 +787,80 @@ static int mvebu_pwm_probe(struct platform_device *pdev, >> struct device *dev = &pdev->dev; >> struct mvebu_pwm *mvpwm; >> void __iomem *base; >> + u32 offset; >> u32 set; >> >> - if (!of_device_is_compatible(mvchip->chip.of_node, >> - "marvell,armada-370-gpio")) >> - return 0; >> - >> - /* >> - * There are only two sets of PWM configuration registers for >> - * all the GPIO lines on those SoCs which this driver reserves >> - * for the first two GPIO chips. So if the resource is missing >> - * we can't treat it as an error. >> - */ >> - if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) >> + if (of_device_is_compatible(mvchip->chip.of_node, >> + "marvell,armada-370-gpio")) { >> + /* >> + * There are only two sets of PWM configuration registers for >> + * all the GPIO lines on those SoCs which this driver reserves >> + * for the first two GPIO chips. So if the resource is missing >> + * we can't treat it as an error. >> + */ >> + if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) >> + return 0; >> + offset = 0; >> + } else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { >> + int ret = of_property_read_u32(dev->of_node, "pwm-offset", >> + &offset); >> + if (ret < 0) >> + return 0; > > It would look more uniform if this was > > if (of_device_is_compatible(mvchip->chip.of_node, > "marvell,armada-8k-gpio")) { Right. However I use soc_variant again below. I think that of_device_is_compatible is too verbose for that. In fact, I'd rather use soc_variant for marvell,armada-370-gpio as well. The trouble is that marvell,armada-370-gpio is not equivalent to MVEBU_GPIO_SOC_VARIANT_ORION. Changing that is more intrusive. >> + } else { >> return 0; >> + } [snip] >> @@ -1200,6 +1235,13 @@ static int mvebu_gpio_probe(struct platform_device *pdev) >> >> devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); >> >> + /* Some MVEBU SoCs have simple PWM support for GPIO lines */ >> + if (IS_ENABLED(CONFIG_PWM)) { >> + err = mvebu_pwm_probe(pdev, mvchip, id); >> + if (err) >> + return err; >> + } >> + > > The existing error handling looks odd here. Why is there no goto > err_domain when probing the PWMs fails? I wonder if this a bug from me > from a long time again? What would you release under the err_domain label? As far as I can see all resources are allocated using devres, and released automatically on failure exit. baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il - _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel