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Tue, 28 Jan 2025 11:29:18 +0000 Received: from GV1PR03MB10456.eurprd03.prod.outlook.com ([fe80::a41e:5aa8:e298:757e]) by GV1PR03MB10456.eurprd03.prod.outlook.com ([fe80::a41e:5aa8:e298:757e%6]) with mapi id 15.20.8377.021; Tue, 28 Jan 2025 11:29:18 +0000 From: Volodymyr Babchuk To: Marc Zyngier CC: "kvmarm@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "kvm@vger.kernel.org" , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Bjorn Andersson , Christoffer Dall , Ganapatrao Kulkarni , Chase Conklin , Eric Auger , Dmytro Terletskyi , Wei-Lin Chang Subject: Re: [PATCH v2 02/12] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Thread-Topic: [PATCH v2 02/12] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Thread-Index: AQHbcAaOrTBbbSLpA0ukEQZvbJQCdQ== Date: Tue, 28 Jan 2025 11:29:18 +0000 Message-ID: <87a5bb18j7.fsf@epam.com> References: <20241217142321.763801-1-maz@kernel.org> <20241217142321.763801-3-maz@kernel.org> <87frl51tse.fsf@epam.com> <86h65kuqia.wl-maz@kernel.org> In-Reply-To: <86h65kuqia.wl-maz@kernel.org> (Marc Zyngier's message of "Mon, 27 Jan 2025 17:15:57 +0000") Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 274ec27f-e2ad-4e7a-7a16-08dd3f8f00b7 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jan 2025 11:29:18.0756 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DDRPeYjNf6Y4Hqp6pYMAwSfyLQubh7wGCG9rEd75APPfIYQJbt1rAOF8gSt8lsk5KGod+Q7zYqLbTJduady988wBUrgl8f1ulL5gn97Q4I0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7773 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250128_032930_239396_C7A59259 X-CRM114-Status: GOOD ( 34.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, Marc Zyngier writes: > + Wei-Lin Chang, who spotted something similar 3 weeks ago, that I > didn't manage to investigate in time. > > On Sun, 26 Jan 2025 15:25:39 +0000, > Volodymyr Babchuk wrote: >>=20 >>=20 >> Hi Marc, >>=20 >> Thank you for these patches. We (myself and Dmytro Terletskyi) are >> trying to use this series to launch up Xen on Amazon Graviton 4 platform= . >> Graviton 4 is built on Neoverse V2 cores and does **not** support >> FEAT_ECV. Looks like we have found issue in this particular patch on >> this particular setup. >>=20 >> Marc Zyngier writes: >>=20 >> > Emulating the timers with FEAT_NV2 is a bit odd, as the timers >> > can be reconfigured behind our back without the hypervisor even >> > noticing. In the VHE case, that's an actual regression in the >> > architecture... >> > >> > Co-developed-by: Christoffer Dall >> > Signed-off-by: Christoffer Dall >> > Signed-off-by: Marc Zyngier >> > --- >> > arch/arm64/kvm/arch_timer.c | 44 +++++++++++++++++++++++++++++++++++= + >> > arch/arm64/kvm/arm.c | 3 +++ >> > include/kvm/arm_arch_timer.h | 1 + >> > 3 files changed, 48 insertions(+) >> > >> > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c >> > index 1215df5904185..ee5f732fbbece 100644 >> > --- a/arch/arm64/kvm/arch_timer.c >> > +++ b/arch/arm64/kvm/arch_timer.c >> > @@ -905,6 +905,50 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) >> > kvm_timer_blocking(vcpu); >> > } >> > =20 >> > +void kvm_timer_sync_nested(struct kvm_vcpu *vcpu) >> > +{ >> > + /* >> > + * When NV2 is on, guest hypervisors have their EL1 timer register >> > + * accesses redirected to the VNCR page. Any guest action taken on >> > + * the timer is postponed until the next exit, leading to a very >> > + * poor quality of emulation. >> > + */ >> > + if (!is_hyp_ctxt(vcpu)) >> > + return; >> > + >> > + if (!vcpu_el2_e2h_is_set(vcpu)) { >> > + /* >> > + * A non-VHE guest hypervisor doesn't have any direct access >> > + * to its timers: the EL2 registers trap (and the HW is >> > + * fully emulated), while the EL0 registers access memory >> > + * despite the access being notionally direct. Boo. >> > + * >> > + * We update the hardware timer registers with the >> > + * latest value written by the guest to the VNCR page >> > + * and let the hardware take care of the rest. >> > + */ >> > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTV_CTL_EL0), SYS_CNTV_CTL)= ; >> > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTV_CVAL_EL0), SYS_CNTV_CVAL= ); >> > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTP_CTL_EL0), SYS_CNTP_CTL)= ; >> > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTP_CVAL_EL0), SYS_CNTP_CVAL= ); >>=20 >>=20 >> Here you are overwriting trapped/emulated state of EL2 vtimer with EL0 >> vtimer, which renders all writes to EL2 timer registers useless. >>=20 >> This is the behavior we observed: >>=20 >> 1. Xen writes to CNTHP_CVAL_EL2, which is trapped and handled in >> kvm_arm_timer_write_sysreg(). >>=20 >> 2. timer_set_cval() updates __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) >>=20 >> 3. timer_restore_state() updates real CNTP_CVAL_EL0 with value from >> __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) >>=20 >> (so far so good) >>=20 >> 4. kvm_timer_sync_nested() is called and it updates real CNTP_CVAL_EL0 >> with __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0), overwriting value that we got >> from Xen. >>=20 >> The same stands for other hypervisor timer registers of course. >>=20 >> I am wondering, what is the correct fix for this issue? >>=20 >> Also, we are observing issues with timers in Dom0, which seems related >> to this, but we didn't pinpoint exact problem yet. > > Thanks for the great debug above, much appreciated. > > As Wei-Lin pointed out in their email[1], there is a copious amount of > nonsense here. This is due to leftovers from the mix of NV+NV2 that > KVM was initially trying to handle before switching to NV2 only. > > The whole VHE vs nVHE makes no sense at all, and both should have the > same behaviour. The only difference is around what gets trapped, and > what doesn't. > > Finally, this crap is masking a subtle bug in timer_emulate(), where > we return too early on updating the IRQ state, hence failing to > publish the interrupt state. > > Could you please give the hack below a go with your setup and report > whether it solves this particular issue? Thanks! This is exactly what we needed. Your suggested changes fixed both issues: in Xen and in Dom0. [...] --=20 WBR, Volodymyr=