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Sat, 14 Dec 2024 10:56:14 +0000 Date: Sat, 14 Dec 2024 10:56:13 +0000 Message-ID: <87a5cysfci.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Peter Collingbourne , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu() In-Reply-To: <20241214-arm64-fix-boot-cpu-smidr-v1-1-0745c40772dd@kernel.org> References: <20241214-arm64-fix-boot-cpu-smidr-v1-1-0745c40772dd@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, pcc@google.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241214_025619_194629_33ACB748 X-CRM114-Status: GOOD ( 33.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [+ Mark] On Sat, 14 Dec 2024 00:52:08 +0000, Mark Brown wrote: > > In commit 892f7237b3ff ("arm64: Delay initialisation of > cpuinfo_arm64::reg_{zcr,smcr}") we moved access to ZCR, SMCR and SMIDR > later in the boot process in order to ensure that we don't attempt to > interact with them if SVE or SME is disabled on the command line. > Unfortunately when initialising the boot CPU in init_cpu_features() we work > on a copy of the struct cpuinfo_arm64 for the boot CPU used only during > boot, not the percpu copy used by the sysfs code. > > Fix this by moving the handling for SMIDR_EL1 for the boot CPU to > cpuinfo_store_boot_cpu() so it can operate on the percpu copy of the data. > This reduces the potential for error that could come from having both the > percpu and boot CPU copies in init_cpu_features(). > > This issue wasn't apparent when testing on emulated platforms that do not > report values in this ID register. > > Fixes: 892f7237b3ff ("arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr}") > Signed-off-by: Mark Brown > Cc: stable@vger.kernel.org > --- > arch/arm64/kernel/cpufeature.c | 6 ------ > arch/arm64/kernel/cpuinfo.c | 11 +++++++++++ > 2 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6ce71f444ed84f9056196bb21bbfac61c9687e30..b88102fd2c20f77e25af6df513fda09a484e882e 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1167,12 +1167,6 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) > id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { > unsigned long cpacr = cpacr_save_enable_kernel_sme(); > > - /* > - * We mask out SMPS since even if the hardware > - * supports priorities the kernel does not at present > - * and we block access to them. > - */ > - info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; > vec_init_vq_map(ARM64_VEC_SME); > > cpacr_restore(cpacr); > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index d79e88fccdfce427507e7a34c5959ce6309cbd12..b7d403da71e5a01ed3943eb37e7a00af238771a2 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -499,4 +499,15 @@ void __init cpuinfo_store_boot_cpu(void) > > boot_cpu_data = *info; > init_cpu_features(&boot_cpu_data); > + > + /* SMIDR_EL1 needs to be stored in the percpu data for sysfs */ > + if (IS_ENABLED(CONFIG_ARM64_SME) && > + id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { > + /* > + * We mask out SMPS since even if the hardware > + * supports priorities the kernel does not at present > + * and we block access to them. > + */ > + info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; > + } > } I don't understand the need to single out SMIDR_EL1. It seems to only make things even more fragile than they already are by adding more synchronisation phases. Why isn't the following a good enough fix? It makes it plain that boot_cpu_data is only a copy of CPU0's initial boot state. diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index d79e88fccdfce..0cbb42fd48850 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -497,6 +497,6 @@ void __init cpuinfo_store_boot_cpu(void) struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); __cpuinfo_store_cpu(info); + init_cpu_features(info); boot_cpu_data = *info; - init_cpu_features(&boot_cpu_data); } Thanks, M. -- Without deviation from the norm, progress is not possible.