* [PATCH 1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map
Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
Cc: stable@vger.kernel.org # 5.10+
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
am65xx-evm Log: https://gist.github.com/nmenon/7e086c4d96d928429b9cd987a6e16b82
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ce8bb4a61011..e749343acced 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -35,7 +35,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index a58a39fa42db..c538a0bf3cdd 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -86,6 +86,7 @@ cbass_main: bus@100000 {
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/5] arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Cc: stable@vger.kernel.org # 5.10+
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
j721e-sk: https://gist.github.com/nmenon/db3f29f2f241f1b5294c7e4054c3fbf1
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 599861259a30..db0669985e42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -76,7 +76,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 4a3872fce533..0e23886c9fd1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -139,6 +139,7 @@ cbass_main: bus@100000 {
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/5] arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: " Nishanth Menon
2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
j7200-evm: https://gist.github.com/nmenon/23a7844a794a0123af9b211eee2b7d0b
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 05a627ad6cdc..16684a2f054d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -54,7 +54,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 64fef4e67d76..b6da0454cc5b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -129,6 +129,7 @@ cbass_main: bus@100000 {
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/5] arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
` (2 preceding siblings ...)
2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map
Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
AM64xx-sk: https://gist.github.com/nmenon/75d413e53005fabc4bde8a4efe227594
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 0c9f3bce8418..f64b368c6c37 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -59,7 +59,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ <0x00 0x01840000 0x00 0xC0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 84bd07cd1824..e88349846871 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -89,6 +89,7 @@ cbass_main: bus@f4000 {
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
--
2.31.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
` (3 preceding siblings ...)
2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon
@ 2022-02-15 20:10 ` Nishanth Menon
2022-02-16 9:16 ` [PATCH 0/5] arm64: dts: ti: k3*: " Marc Zyngier
2022-02-22 19:31 ` Nishanth Menon
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-15 20:10 UTC (permalink / raw)
To: Tero Kristo, Vignesh Raghavendra, Marc Zyngier
Cc: linux-kernel, devicetree, linux-arm-kernel, Krzysztof Kozlowski,
Rob Herring, Nishanth Menon, stable
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: stable@vger.kernel.org
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Testing: based on next-20220215
J721s2-evm Log: https://gist.github.com/nmenon/302b0bcfbb1b5b8743fa5c242eb7d15f
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++-
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b04db1d3ab61..be7f39299894 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -34,7 +34,10 @@ gic500: interrupt-controller@1800000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
- <0x00 0x01900000 0x00 0x100000>; /* GICR */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index fe5234c40f6c..7b930a85a29d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -119,6 +119,7 @@ cbass_main: bus@100000 {
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
` (4 preceding siblings ...)
2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon
@ 2022-02-16 9:16 ` Marc Zyngier
2022-02-22 19:31 ` Nishanth Menon
6 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2022-02-16 9:16 UTC (permalink / raw)
To: Nishanth Menon
Cc: Tero Kristo, Vignesh Raghavendra, linux-kernel, devicetree,
linux-arm-kernel, Krzysztof Kozlowski, Rob Herring
On Tue, 15 Feb 2022 20:10:03 +0000,
Nishanth Menon <nm@ti.com> wrote:
>
> Hi,
>
> This series was triggered by the discussion in [1], and we realized we
> need to cleanup the definitions in K3 SoC. Usage of kvm with gic-v2
> compatibility is a bit niche usecase, but valid and possible with A53
> and A72 even though the GIC500 instantiation is done with no backward
> compatibility.
>
> Nishanth Menon (5):
> arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++-
> arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 +
> 10 files changed, 25 insertions(+), 5 deletions(-)
>
> [1] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
For the series:
Acked-by: Marc Zyngier <maz@kernel.org>
M.
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs
2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon
` (5 preceding siblings ...)
2022-02-16 9:16 ` [PATCH 0/5] arm64: dts: ti: k3*: " Marc Zyngier
@ 2022-02-22 19:31 ` Nishanth Menon
6 siblings, 0 replies; 8+ messages in thread
From: Nishanth Menon @ 2022-02-22 19:31 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Marc Zyngier, Vignesh Raghavendra
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel, devicetree,
linux-kernel
Hi Nishanth Menon,
On Tue, 15 Feb 2022 14:10:03 -0600, Nishanth Menon wrote:
> This series was triggered by the discussion in [1], and we realized we
> need to cleanup the definitions in K3 SoC. Usage of kvm with gic-v2
> compatibility is a bit niche usecase, but valid and possible with A53
> and A72 even though the GIC500 instantiation is done with no backward
> compatibility.
>
> Nishanth Menon (5):
> arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
> arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
commit: 8cae268b70f387ff9e697ccd62fb2384079124e7
[2/5] arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
commit: a06ed27f3bc63ab9e10007dc0118d910908eb045
[3/5] arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
commit: 1a307cc299430dd7139d351a3b8941f493dfa885
[4/5] arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
commit: de60edf1be3d42d4a1b303b41c7c53b2f865726e
[5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
commit: a966803781fc5e1875511db9392b0d16174c5dd2
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 8+ messages in thread