* [PATCH 01/12] OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 02/12] OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck Paul Walmsley
` (12 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
The gating of pad_clks and slimbus_ck is controlled by the PRCM, but
since the clock source is external, this is the SW responsability
to gate / un-gate it when the mcpdm or slimbus module need to be used.
There is no autogating possible with such external clock.
Add SW control to enable / disable this SW gating in the pad_clks_ck
and slimbus_clk clock node.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index bfcd19f..828d7f4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -47,7 +47,9 @@ static struct clk extalt_clkin_ck = {
static struct clk pad_clks_ck = {
.name = "pad_clks_ck",
.rate = 12000000,
- .ops = &clkops_null,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+ .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
};
static struct clk pad_slimbus_core_clks_ck = {
@@ -65,7 +67,9 @@ static struct clk secure_32k_clk_src_ck = {
static struct clk slimbus_clk = {
.name = "slimbus_clk",
.rate = 12000000,
- .ops = &clkops_null,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+ .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
};
static struct clk sys_32k_ck = {
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 02/12] OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
2010-12-14 6:34 ` [PATCH 01/12] OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes Paul Walmsley
` (11 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
The smartreflex modules belong to an ALWON_FCLK clock domain that
does not have any SW control. The gating of that interface clock
is triggered by a transition of the WKUP clock domain to idle.
Attach both smartreflex instances on OMAP3 to the WKUP clock domain.
The missing clock domain field in srX_fck clock nodes was reported by
Kevin during the discussion about smartreflex on OMAP3:
https://patchwork.kernel.org/patch/199342/
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
---
arch/arm/mach-omap2/clock3xxx_data.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 0579604..94cbae3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3044,6 +3044,7 @@ static struct clk sr1_fck = {
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
@@ -3054,6 +3055,7 @@ static struct clk sr2_fck = {
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
2010-12-14 6:34 ` [PATCH 01/12] OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk Paul Walmsley
2010-12-14 6:34 ` [PATCH 02/12] OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-22 1:47 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 04/12] OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ck Paul Walmsley
` (10 subsequent siblings)
13 siblings, 1 reply; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Thara Gopinath <thara@ti.com>
This patch extends the OMAP4 clock data to include
various x2 clock nodes between DPLL and HS dividers as the
clock framework skips a x2 while calculating the dpll locked
frequency.
The clock database extensions are autogenerated using
the scripts maintained by Benoit Cousson.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Thara Gopinath <thara@ti.com>
[paul at pwsan.com: fixed merge conflicts against v2.6.37-rc5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 423 ++++++++++++++++++++--------------
1 files changed, 248 insertions(+), 175 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 828d7f4..aa503cb 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -269,11 +269,63 @@ static struct clk dpll_abe_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
+static struct clk dpll_abe_x2_ck = {
+ .name = "dpll_abe_x2_ck",
+ .parent = &dpll_abe_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m2x2_div[] = {
+ { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_abe_m2x2_ck = {
.name = "dpll_abe_m2x2_ck",
- .parent = &dpll_abe_ck,
+ .parent = &dpll_abe_x2_ck,
+ .clksel = dpll_abe_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
};
static struct clk abe_24m_fclk = {
@@ -330,50 +382,10 @@ static struct clk aess_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
-static const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 },
- { .div = 2, .val = 2, .flags = RATE_IN_4430 },
- { .div = 3, .val = 3, .flags = RATE_IN_4430 },
- { .div = 4, .val = 4, .flags = RATE_IN_4430 },
- { .div = 5, .val = 5, .flags = RATE_IN_4430 },
- { .div = 6, .val = 6, .flags = RATE_IN_4430 },
- { .div = 7, .val = 7, .flags = RATE_IN_4430 },
- { .div = 8, .val = 8, .flags = RATE_IN_4430 },
- { .div = 9, .val = 9, .flags = RATE_IN_4430 },
- { .div = 10, .val = 10, .flags = RATE_IN_4430 },
- { .div = 11, .val = 11, .flags = RATE_IN_4430 },
- { .div = 12, .val = 12, .flags = RATE_IN_4430 },
- { .div = 13, .val = 13, .flags = RATE_IN_4430 },
- { .div = 14, .val = 14, .flags = RATE_IN_4430 },
- { .div = 15, .val = 15, .flags = RATE_IN_4430 },
- { .div = 16, .val = 16, .flags = RATE_IN_4430 },
- { .div = 17, .val = 17, .flags = RATE_IN_4430 },
- { .div = 18, .val = 18, .flags = RATE_IN_4430 },
- { .div = 19, .val = 19, .flags = RATE_IN_4430 },
- { .div = 20, .val = 20, .flags = RATE_IN_4430 },
- { .div = 21, .val = 21, .flags = RATE_IN_4430 },
- { .div = 22, .val = 22, .flags = RATE_IN_4430 },
- { .div = 23, .val = 23, .flags = RATE_IN_4430 },
- { .div = 24, .val = 24, .flags = RATE_IN_4430 },
- { .div = 25, .val = 25, .flags = RATE_IN_4430 },
- { .div = 26, .val = 26, .flags = RATE_IN_4430 },
- { .div = 27, .val = 27, .flags = RATE_IN_4430 },
- { .div = 28, .val = 28, .flags = RATE_IN_4430 },
- { .div = 29, .val = 29, .flags = RATE_IN_4430 },
- { .div = 30, .val = 30, .flags = RATE_IN_4430 },
- { .div = 31, .val = 31, .flags = RATE_IN_4430 },
- { .div = 0 },
-};
-
-static const struct clksel dpll_abe_m3_div[] = {
- { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-static struct clk dpll_abe_m3_ck = {
- .name = "dpll_abe_m3_ck",
- .parent = &dpll_abe_ck,
- .clksel = dpll_abe_m3_div,
+static struct clk dpll_abe_m3x2_ck = {
+ .name = "dpll_abe_m3x2_ck",
+ .parent = &dpll_abe_x2_ck,
+ .clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -384,7 +396,7 @@ static struct clk dpll_abe_m3_ck = {
static const struct clksel core_hsd_byp_clk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -428,15 +440,22 @@ static struct clk dpll_core_ck = {
.recalc = &omap3_dpll_recalc,
};
-static const struct clksel dpll_core_m6_div[] = {
- { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+static struct clk dpll_core_x2_ck = {
+ .name = "dpll_core_x2_ck",
+ .parent = &dpll_core_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_core_m6x2_div[] = {
+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
-static struct clk dpll_core_m6_ck = {
- .name = "dpll_core_m6_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m6x2_ck = {
+ .name = "dpll_core_m6x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
@@ -447,7 +466,7 @@ static struct clk dpll_core_m6_ck = {
static const struct clksel dbgclk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -458,10 +477,15 @@ static struct clk dbgclk_mux_ck = {
.recalc = &followparent_recalc,
};
+static const struct clksel dpll_core_m2_div[] = {
+ { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_core_m2_ck = {
.name = "dpll_core_m2_ck",
.parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+ .clksel = dpll_core_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
@@ -477,10 +501,10 @@ static struct clk ddrphy_ck = {
.recalc = &followparent_recalc,
};
-static struct clk dpll_core_m5_ck = {
- .name = "dpll_core_m5_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m5x2_ck = {
+ .name = "dpll_core_m5x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -490,13 +514,13 @@ static struct clk dpll_core_m5_ck = {
};
static const struct clksel div_core_div[] = {
- { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+ { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
{ .parent = NULL },
};
static struct clk div_core_ck = {
.name = "div_core_ck",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_core_div,
.clksel_reg = OMAP4430_CM_CLKSEL_CORE,
.clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
@@ -515,13 +539,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
};
static const struct clksel div_iva_hs_clk_div[] = {
- { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+ { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
{ .parent = NULL },
};
static struct clk div_iva_hs_clk = {
.name = "div_iva_hs_clk",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_iva_hs_clk_div,
.clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
.clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -533,7 +557,7 @@ static struct clk div_iva_hs_clk = {
static struct clk div_mpu_hs_clk = {
.name = "div_mpu_hs_clk",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_iva_hs_clk_div,
.clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
.clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -543,10 +567,10 @@ static struct clk div_mpu_hs_clk = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m4_ck = {
- .name = "dpll_core_m4_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m4x2_ck = {
+ .name = "dpll_core_m4x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -557,15 +581,20 @@ static struct clk dpll_core_m4_ck = {
static struct clk dll_clk_div_ck = {
.name = "dll_clk_div_ck",
- .parent = &dpll_core_m4_ck,
+ .parent = &dpll_core_m4x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
+static const struct clksel dpll_abe_m2_div[] = {
+ { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_abe_m2_ck = {
.name = "dpll_abe_m2_ck",
.parent = &dpll_abe_ck,
- .clksel = dpll_abe_m3_div,
+ .clksel = dpll_abe_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
@@ -574,10 +603,10 @@ static struct clk dpll_abe_m2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m3_ck = {
- .name = "dpll_core_m3_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m3x2_ck = {
+ .name = "dpll_core_m3x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -586,10 +615,10 @@ static struct clk dpll_core_m3_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m7_ck = {
- .name = "dpll_core_m7_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m7x2_ck = {
+ .name = "dpll_core_m7x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
@@ -642,15 +671,22 @@ static struct clk dpll_iva_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
-static const struct clksel dpll_iva_m4_div[] = {
- { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+static struct clk dpll_iva_x2_ck = {
+ .name = "dpll_iva_x2_ck",
+ .parent = &dpll_iva_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_iva_m4x2_div[] = {
+ { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
-static struct clk dpll_iva_m4_ck = {
- .name = "dpll_iva_m4_ck",
- .parent = &dpll_iva_ck,
- .clksel = dpll_iva_m4_div,
+static struct clk dpll_iva_m4x2_ck = {
+ .name = "dpll_iva_m4x2_ck",
+ .parent = &dpll_iva_x2_ck,
+ .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -659,10 +695,10 @@ static struct clk dpll_iva_m4_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_iva_m5_ck = {
- .name = "dpll_iva_m5_ck",
- .parent = &dpll_iva_ck,
- .clksel = dpll_iva_m4_div,
+static struct clk dpll_iva_m5x2_ck = {
+ .name = "dpll_iva_m5x2_ck",
+ .parent = &dpll_iva_x2_ck,
+ .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -719,9 +755,16 @@ static struct clk dpll_mpu_m2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
+static struct clk dpll_mpu_x2_ck = {
+ .name = "dpll_mpu_x2_ck",
+ .parent = &dpll_mpu_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
static struct clk per_hs_clk_div_ck = {
.name = "per_hs_clk_div_ck",
- .parent = &dpll_abe_m3_ck,
+ .parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
@@ -791,17 +834,34 @@ static struct clk dpll_per_m2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
+static struct clk dpll_per_x2_ck = {
+ .name = "dpll_per_x2_ck",
+ .parent = &dpll_per_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_per_m2x2_div[] = {
+ { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_per_m2x2_ck = {
.name = "dpll_per_m2x2_ck",
- .parent = &dpll_per_ck,
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m3_ck = {
- .name = "dpll_per_m3_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m3x2_ck = {
+ .name = "dpll_per_m3x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -810,10 +870,10 @@ static struct clk dpll_per_m3_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m4_ck = {
- .name = "dpll_per_m4_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m4x2_ck = {
+ .name = "dpll_per_m4x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -822,10 +882,10 @@ static struct clk dpll_per_m4_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m5_ck = {
- .name = "dpll_per_m5_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m5x2_ck = {
+ .name = "dpll_per_m5x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -834,10 +894,10 @@ static struct clk dpll_per_m5_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m6_ck = {
- .name = "dpll_per_m6_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m6x2_ck = {
+ .name = "dpll_per_m6x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
@@ -846,10 +906,10 @@ static struct clk dpll_per_m6_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m7_ck = {
- .name = "dpll_per_m7_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m7x2_ck = {
+ .name = "dpll_per_m7x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
@@ -889,14 +949,21 @@ static struct clk dpll_unipro_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
+static struct clk dpll_unipro_x2_ck = {
+ .name = "dpll_unipro_x2_ck",
+ .parent = &dpll_unipro_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
static const struct clksel dpll_unipro_m2x2_div[] = {
- { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+ { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
static struct clk dpll_unipro_m2x2_ck = {
.name = "dpll_unipro_m2x2_ck",
- .parent = &dpll_unipro_ck,
+ .parent = &dpll_unipro_x2_ck,
.clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -908,7 +975,7 @@ static struct clk dpll_unipro_m2x2_ck = {
static struct clk usb_hs_clk_div_ck = {
.name = "usb_hs_clk_div_ck",
- .parent = &dpll_abe_m3_ck,
+ .parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
@@ -971,7 +1038,7 @@ static struct clk dpll_usb_m2_ck = {
static const struct clksel ducati_clk_mux_sel[] = {
{ .parent = &div_core_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -1044,13 +1111,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
};
static const struct clksel func_64m_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
{ .parent = NULL },
};
static struct clk func_64m_fclk = {
.name = "func_64m_fclk",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = func_64m_fclk_div,
.clksel_reg = OMAP4430_CM_SCALE_FCLK,
.clksel_mask = OMAP4430_SCALE_FCLK_MASK,
@@ -1224,7 +1291,7 @@ static struct clk per_abe_24m_fclk = {
static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
{ .parent = NULL },
};
@@ -1358,7 +1425,7 @@ static struct clk dsp_fck = {
.enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "tesla_clkdm",
- .parent = &dpll_iva_m4_ck,
+ .parent = &dpll_iva_m4x2_ck,
.recalc = &followparent_recalc,
};
@@ -1388,7 +1455,7 @@ static struct clk dss_dss_clk = {
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
- .parent = &dpll_per_m5_ck,
+ .parent = &dpll_per_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -1445,14 +1512,14 @@ static struct clk emif2_fck = {
};
static const struct clksel fdif_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
/* Merged fdif_fclk into fdif */
static struct clk fdif_fck = {
.name = "fdif_fck",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = fdif_fclk_div,
.clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1606,15 +1673,15 @@ static struct clk gpmc_ick = {
};
static const struct clksel sgx_clk_mux_sel[] = {
- { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+ { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
/* Merged sgx_clk_mux into gpu */
static struct clk gpu_fck = {
.name = "gpu_fck",
- .parent = &dpll_core_m7_ck,
+ .parent = &dpll_core_m7x2_ck,
.clksel = sgx_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
@@ -1733,7 +1800,7 @@ static struct clk iva_fck = {
.enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ivahd_clkdm",
- .parent = &dpll_iva_m5_ck,
+ .parent = &dpll_iva_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -2097,7 +2164,7 @@ static struct clk sl2if_ick = {
.enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ivahd_clkdm",
- .parent = &dpll_iva_m5_ck,
+ .parent = &dpll_iva_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -2442,36 +2509,6 @@ static struct clk usb_host_fs_fck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_host_hs_utmi_p3_clk = {
- .name = "usb_host_hs_utmi_p3_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p1_clk = {
- .name = "usb_host_hs_hsic60m_p1_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p2_clk = {
- .name = "usb_host_hs_hsic60m_p2_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
static const struct clksel utmi_p1_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
@@ -2526,6 +2563,16 @@ static struct clk usb_host_hs_utmi_p2_clk = {
.recalc = &followparent_recalc,
};
+static struct clk usb_host_hs_utmi_p3_clk = {
+ .name = "usb_host_hs_utmi_p3_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
static struct clk usb_host_hs_hsic480m_p1_clk = {
.name = "usb_host_hs_hsic480m_p1_clk",
.ops = &clkops_omap2_dflt,
@@ -2536,6 +2583,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
.recalc = &followparent_recalc,
};
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+ .name = "usb_host_hs_hsic60m_p1_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+ .name = "usb_host_hs_hsic60m_p2_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
static struct clk usb_host_hs_hsic480m_p2_clk = {
.name = "usb_host_hs_hsic480m_p2_clk",
.ops = &clkops_omap2_dflt,
@@ -2660,13 +2727,13 @@ static const struct clksel_rate div2_14to18_rates[] = {
};
static const struct clksel usim_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
{ .parent = NULL },
};
static struct clk usim_ck = {
.name = "usim_ck",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = usim_fclk_div,
.clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
@@ -2778,43 +2845,49 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
CLK(NULL, "abe_clk", &abe_clk, CK_443X),
CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
- CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
+ CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
+ CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
+ CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
- CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
- CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
+ CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
+ CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
- CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
- CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
+ CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
+ CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
+ CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
+ CLK(NULL, "dpll_mpu_x2_ck", &dpll_mpu_x2_ck, CK_443X),
CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
- CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
- CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
- CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
- CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
- CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
+ CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
+ CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
@@ -2942,14 +3015,14 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("ehci-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
- CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
- CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes
2010-12-14 6:34 ` [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes Paul Walmsley
@ 2010-12-22 1:47 ` Paul Walmsley
2010-12-30 4:52 ` Gopinath, Thara
0 siblings, 1 reply; 24+ messages in thread
From: Paul Walmsley @ 2010-12-22 1:47 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 13 Dec 2010, Paul Walmsley wrote:
> From: Thara Gopinath <thara@ti.com>
>
> This patch extends the OMAP4 clock data to include
> various x2 clock nodes between DPLL and HS dividers as the
> clock framework skips a x2 while calculating the dpll locked
> frequency.
>
> The clock database extensions are autogenerated using
> the scripts maintained by Benoit Cousson.
>
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Signed-off-by: Thara Gopinath <thara@ti.com>
> [paul at pwsan.com: fixed merge conflicts against v2.6.37-rc5]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
This patch has been updated to drop dpll_mpu_x2_ck. According to Beno?t
there is no need for this clock because there are no users of it, and the
script has been updated accordingly.
- Paul
From: Thara Gopinath <thara@ti.com>
Date: Tue, 21 Dec 2010 18:11:05 -0700
Subject: [PATCH] OMAP4: clock data: Add missing DPLL x2 clock nodes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch extends the OMAP4 clock data to include
various x2 clock nodes between DPLL and HS dividers as the
clock framework skips a x2 while calculating the dpll locked
frequency.
The clock database extensions are autogenerated using
the scripts maintained by Benoit Cousson.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Thara Gopinath <thara@ti.com>
[paul at pwsan.com: fixed merge conflicts against v2.6.37-rc5; dropped
dpll_mpu_x2_ck on advice from Beno?t]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 415 ++++++++++++++++++++--------------
1 files changed, 240 insertions(+), 175 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 305019c4..7c8d7f4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -275,11 +275,63 @@ static struct clk dpll_abe_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
+static struct clk dpll_abe_x2_ck = {
+ .name = "dpll_abe_x2_ck",
+ .parent = &dpll_abe_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m2x2_div[] = {
+ { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_abe_m2x2_ck = {
.name = "dpll_abe_m2x2_ck",
- .parent = &dpll_abe_ck,
+ .parent = &dpll_abe_x2_ck,
+ .clksel = dpll_abe_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
};
static struct clk abe_24m_fclk = {
@@ -336,50 +388,10 @@ static struct clk aess_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
-static const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 },
- { .div = 2, .val = 2, .flags = RATE_IN_4430 },
- { .div = 3, .val = 3, .flags = RATE_IN_4430 },
- { .div = 4, .val = 4, .flags = RATE_IN_4430 },
- { .div = 5, .val = 5, .flags = RATE_IN_4430 },
- { .div = 6, .val = 6, .flags = RATE_IN_4430 },
- { .div = 7, .val = 7, .flags = RATE_IN_4430 },
- { .div = 8, .val = 8, .flags = RATE_IN_4430 },
- { .div = 9, .val = 9, .flags = RATE_IN_4430 },
- { .div = 10, .val = 10, .flags = RATE_IN_4430 },
- { .div = 11, .val = 11, .flags = RATE_IN_4430 },
- { .div = 12, .val = 12, .flags = RATE_IN_4430 },
- { .div = 13, .val = 13, .flags = RATE_IN_4430 },
- { .div = 14, .val = 14, .flags = RATE_IN_4430 },
- { .div = 15, .val = 15, .flags = RATE_IN_4430 },
- { .div = 16, .val = 16, .flags = RATE_IN_4430 },
- { .div = 17, .val = 17, .flags = RATE_IN_4430 },
- { .div = 18, .val = 18, .flags = RATE_IN_4430 },
- { .div = 19, .val = 19, .flags = RATE_IN_4430 },
- { .div = 20, .val = 20, .flags = RATE_IN_4430 },
- { .div = 21, .val = 21, .flags = RATE_IN_4430 },
- { .div = 22, .val = 22, .flags = RATE_IN_4430 },
- { .div = 23, .val = 23, .flags = RATE_IN_4430 },
- { .div = 24, .val = 24, .flags = RATE_IN_4430 },
- { .div = 25, .val = 25, .flags = RATE_IN_4430 },
- { .div = 26, .val = 26, .flags = RATE_IN_4430 },
- { .div = 27, .val = 27, .flags = RATE_IN_4430 },
- { .div = 28, .val = 28, .flags = RATE_IN_4430 },
- { .div = 29, .val = 29, .flags = RATE_IN_4430 },
- { .div = 30, .val = 30, .flags = RATE_IN_4430 },
- { .div = 31, .val = 31, .flags = RATE_IN_4430 },
- { .div = 0 },
-};
-
-static const struct clksel dpll_abe_m3_div[] = {
- { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-static struct clk dpll_abe_m3_ck = {
- .name = "dpll_abe_m3_ck",
- .parent = &dpll_abe_ck,
- .clksel = dpll_abe_m3_div,
+static struct clk dpll_abe_m3x2_ck = {
+ .name = "dpll_abe_m3x2_ck",
+ .parent = &dpll_abe_x2_ck,
+ .clksel = dpll_abe_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -390,7 +402,7 @@ static struct clk dpll_abe_m3_ck = {
static const struct clksel core_hsd_byp_clk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -434,15 +446,22 @@ static struct clk dpll_core_ck = {
.recalc = &omap3_dpll_recalc,
};
-static const struct clksel dpll_core_m6_div[] = {
- { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+static struct clk dpll_core_x2_ck = {
+ .name = "dpll_core_x2_ck",
+ .parent = &dpll_core_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_core_m6x2_div[] = {
+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
-static struct clk dpll_core_m6_ck = {
- .name = "dpll_core_m6_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m6x2_ck = {
+ .name = "dpll_core_m6x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
@@ -453,7 +472,7 @@ static struct clk dpll_core_m6_ck = {
static const struct clksel dbgclk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -464,10 +483,15 @@ static struct clk dbgclk_mux_ck = {
.recalc = &followparent_recalc,
};
+static const struct clksel dpll_core_m2_div[] = {
+ { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_core_m2_ck = {
.name = "dpll_core_m2_ck",
.parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+ .clksel = dpll_core_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
@@ -483,10 +507,10 @@ static struct clk ddrphy_ck = {
.recalc = &followparent_recalc,
};
-static struct clk dpll_core_m5_ck = {
- .name = "dpll_core_m5_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m5x2_ck = {
+ .name = "dpll_core_m5x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -496,13 +520,13 @@ static struct clk dpll_core_m5_ck = {
};
static const struct clksel div_core_div[] = {
- { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+ { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
{ .parent = NULL },
};
static struct clk div_core_ck = {
.name = "div_core_ck",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_core_div,
.clksel_reg = OMAP4430_CM_CLKSEL_CORE,
.clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
@@ -521,13 +545,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
};
static const struct clksel div_iva_hs_clk_div[] = {
- { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+ { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
{ .parent = NULL },
};
static struct clk div_iva_hs_clk = {
.name = "div_iva_hs_clk",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_iva_hs_clk_div,
.clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
.clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -539,7 +563,7 @@ static struct clk div_iva_hs_clk = {
static struct clk div_mpu_hs_clk = {
.name = "div_mpu_hs_clk",
- .parent = &dpll_core_m5_ck,
+ .parent = &dpll_core_m5x2_ck,
.clksel = div_iva_hs_clk_div,
.clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
.clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
@@ -549,10 +573,10 @@ static struct clk div_mpu_hs_clk = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m4_ck = {
- .name = "dpll_core_m4_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m4x2_ck = {
+ .name = "dpll_core_m4x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -563,15 +587,20 @@ static struct clk dpll_core_m4_ck = {
static struct clk dll_clk_div_ck = {
.name = "dll_clk_div_ck",
- .parent = &dpll_core_m4_ck,
+ .parent = &dpll_core_m4x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
+static const struct clksel dpll_abe_m2_div[] = {
+ { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_abe_m2_ck = {
.name = "dpll_abe_m2_ck",
.parent = &dpll_abe_ck,
- .clksel = dpll_abe_m3_div,
+ .clksel = dpll_abe_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
@@ -580,10 +609,10 @@ static struct clk dpll_abe_m2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m3_ck = {
- .name = "dpll_core_m3_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m3x2_ck = {
+ .name = "dpll_core_m3x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -592,10 +621,10 @@ static struct clk dpll_core_m3_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_core_m7_ck = {
- .name = "dpll_core_m7_ck",
- .parent = &dpll_core_ck,
- .clksel = dpll_core_m6_div,
+static struct clk dpll_core_m7x2_ck = {
+ .name = "dpll_core_m7x2_ck",
+ .parent = &dpll_core_x2_ck,
+ .clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
@@ -648,15 +677,22 @@ static struct clk dpll_iva_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
-static const struct clksel dpll_iva_m4_div[] = {
- { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+static struct clk dpll_iva_x2_ck = {
+ .name = "dpll_iva_x2_ck",
+ .parent = &dpll_iva_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_iva_m4x2_div[] = {
+ { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
-static struct clk dpll_iva_m4_ck = {
- .name = "dpll_iva_m4_ck",
- .parent = &dpll_iva_ck,
- .clksel = dpll_iva_m4_div,
+static struct clk dpll_iva_m4x2_ck = {
+ .name = "dpll_iva_m4x2_ck",
+ .parent = &dpll_iva_x2_ck,
+ .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -665,10 +701,10 @@ static struct clk dpll_iva_m4_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_iva_m5_ck = {
- .name = "dpll_iva_m5_ck",
- .parent = &dpll_iva_ck,
- .clksel = dpll_iva_m4_div,
+static struct clk dpll_iva_m5x2_ck = {
+ .name = "dpll_iva_m5x2_ck",
+ .parent = &dpll_iva_x2_ck,
+ .clksel = dpll_iva_m4x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -727,7 +763,7 @@ static struct clk dpll_mpu_m2_ck = {
static struct clk per_hs_clk_div_ck = {
.name = "per_hs_clk_div_ck",
- .parent = &dpll_abe_m3_ck,
+ .parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
@@ -797,17 +833,34 @@ static struct clk dpll_per_m2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
+static struct clk dpll_per_x2_ck = {
+ .name = "dpll_per_x2_ck",
+ .parent = &dpll_per_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_per_m2x2_div[] = {
+ { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+ { .parent = NULL },
+};
+
static struct clk dpll_per_m2x2_ck = {
.name = "dpll_per_m2x2_ck",
- .parent = &dpll_per_ck,
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m3_ck = {
- .name = "dpll_per_m3_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m3x2_ck = {
+ .name = "dpll_per_m3x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_null,
@@ -816,10 +869,10 @@ static struct clk dpll_per_m3_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m4_ck = {
- .name = "dpll_per_m4_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m4x2_ck = {
+ .name = "dpll_per_m4x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
.ops = &clkops_null,
@@ -828,10 +881,10 @@ static struct clk dpll_per_m4_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m5_ck = {
- .name = "dpll_per_m5_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m5x2_ck = {
+ .name = "dpll_per_m5x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
.ops = &clkops_null,
@@ -840,10 +893,10 @@ static struct clk dpll_per_m5_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m6_ck = {
- .name = "dpll_per_m6_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m6x2_ck = {
+ .name = "dpll_per_m6x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
.ops = &clkops_null,
@@ -852,10 +905,10 @@ static struct clk dpll_per_m6_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-static struct clk dpll_per_m7_ck = {
- .name = "dpll_per_m7_ck",
- .parent = &dpll_per_ck,
- .clksel = dpll_per_m2_div,
+static struct clk dpll_per_m7x2_ck = {
+ .name = "dpll_per_m7x2_ck",
+ .parent = &dpll_per_x2_ck,
+ .clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
.clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
.ops = &clkops_null,
@@ -895,14 +948,21 @@ static struct clk dpll_unipro_ck = {
.set_rate = &omap3_noncore_dpll_set_rate,
};
+static struct clk dpll_unipro_x2_ck = {
+ .name = "dpll_unipro_x2_ck",
+ .parent = &dpll_unipro_ck,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
static const struct clksel dpll_unipro_m2x2_div[] = {
- { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+ { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
static struct clk dpll_unipro_m2x2_ck = {
.name = "dpll_unipro_m2x2_ck",
- .parent = &dpll_unipro_ck,
+ .parent = &dpll_unipro_x2_ck,
.clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -914,7 +974,7 @@ static struct clk dpll_unipro_m2x2_ck = {
static struct clk usb_hs_clk_div_ck = {
.name = "usb_hs_clk_div_ck",
- .parent = &dpll_abe_m3_ck,
+ .parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
@@ -977,7 +1037,7 @@ static struct clk dpll_usb_m2_ck = {
static const struct clksel ducati_clk_mux_sel[] = {
{ .parent = &div_core_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
@@ -1050,13 +1110,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
};
static const struct clksel func_64m_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
{ .parent = NULL },
};
static struct clk func_64m_fclk = {
.name = "func_64m_fclk",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = func_64m_fclk_div,
.clksel_reg = OMAP4430_CM_SCALE_FCLK,
.clksel_mask = OMAP4430_SCALE_FCLK_MASK,
@@ -1230,7 +1290,7 @@ static struct clk per_abe_24m_fclk = {
static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
{ .parent = NULL },
};
@@ -1364,7 +1424,7 @@ static struct clk dsp_fck = {
.enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "tesla_clkdm",
- .parent = &dpll_iva_m4_ck,
+ .parent = &dpll_iva_m4x2_ck,
.recalc = &followparent_recalc,
};
@@ -1394,7 +1454,7 @@ static struct clk dss_dss_clk = {
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
- .parent = &dpll_per_m5_ck,
+ .parent = &dpll_per_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -1451,14 +1511,14 @@ static struct clk emif2_fck = {
};
static const struct clksel fdif_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
/* Merged fdif_fclk into fdif */
static struct clk fdif_fck = {
.name = "fdif_fck",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = fdif_fclk_div,
.clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1612,15 +1672,15 @@ static struct clk gpmc_ick = {
};
static const struct clksel sgx_clk_mux_sel[] = {
- { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
- { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+ { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
/* Merged sgx_clk_mux into gpu */
static struct clk gpu_fck = {
.name = "gpu_fck",
- .parent = &dpll_core_m7_ck,
+ .parent = &dpll_core_m7x2_ck,
.clksel = sgx_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
@@ -1739,7 +1799,7 @@ static struct clk iva_fck = {
.enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ivahd_clkdm",
- .parent = &dpll_iva_m5_ck,
+ .parent = &dpll_iva_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -2103,7 +2163,7 @@ static struct clk sl2if_ick = {
.enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ivahd_clkdm",
- .parent = &dpll_iva_m5_ck,
+ .parent = &dpll_iva_m5x2_ck,
.recalc = &followparent_recalc,
};
@@ -2448,36 +2508,6 @@ static struct clk usb_host_fs_fck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_host_hs_utmi_p3_clk = {
- .name = "usb_host_hs_utmi_p3_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p1_clk = {
- .name = "usb_host_hs_hsic60m_p1_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p2_clk = {
- .name = "usb_host_hs_hsic60m_p2_clk",
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
- .clkdm_name = "l3_init_clkdm",
- .parent = &init_60m_fclk,
- .recalc = &followparent_recalc,
-};
-
static const struct clksel utmi_p1_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
@@ -2532,6 +2562,16 @@ static struct clk usb_host_hs_utmi_p2_clk = {
.recalc = &followparent_recalc,
};
+static struct clk usb_host_hs_utmi_p3_clk = {
+ .name = "usb_host_hs_utmi_p3_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
static struct clk usb_host_hs_hsic480m_p1_clk = {
.name = "usb_host_hs_hsic480m_p1_clk",
.ops = &clkops_omap2_dflt,
@@ -2542,6 +2582,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
.recalc = &followparent_recalc,
};
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+ .name = "usb_host_hs_hsic60m_p1_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+ .name = "usb_host_hs_hsic60m_p2_clk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+ .clkdm_name = "l3_init_clkdm",
+ .parent = &init_60m_fclk,
+ .recalc = &followparent_recalc,
+};
+
static struct clk usb_host_hs_hsic480m_p2_clk = {
.name = "usb_host_hs_hsic480m_p2_clk",
.ops = &clkops_omap2_dflt,
@@ -2666,13 +2726,13 @@ static const struct clksel_rate div2_14to18_rates[] = {
};
static const struct clksel usim_fclk_div[] = {
- { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+ { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
{ .parent = NULL },
};
static struct clk usim_ck = {
.name = "usim_ck",
- .parent = &dpll_per_m4_ck,
+ .parent = &dpll_per_m4x2_ck,
.clksel = usim_fclk_div,
.clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
@@ -2784,43 +2844,48 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
CLK(NULL, "abe_clk", &abe_clk, CK_443X),
CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
- CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
+ CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
+ CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
+ CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
- CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
- CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
+ CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
+ CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
- CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
- CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
+ CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
+ CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
+ CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
- CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
- CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
- CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
- CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
- CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
+ CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
+ CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
+ CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
@@ -2947,14 +3012,14 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
- CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
- CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
+ CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
--
1.7.2.3
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes
2010-12-22 1:47 ` Paul Walmsley
@ 2010-12-30 4:52 ` Gopinath, Thara
0 siblings, 0 replies; 24+ messages in thread
From: Gopinath, Thara @ 2010-12-30 4:52 UTC (permalink / raw)
To: linux-arm-kernel
>>-----Original Message-----
>>From: Paul Walmsley [mailto:paul at pwsan.com]
>>Sent: Wednesday, December 22, 2010 7:17 AM
>>To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
>>Cc: Gopinath, Thara; Nayak, Rajendra; Cousson, Benoit
>>Subject: Re: [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock
>>nodes
>>
>>On Mon, 13 Dec 2010, Paul Walmsley wrote:
>>
>>> From: Thara Gopinath <thara@ti.com>
>>>
>>> This patch extends the OMAP4 clock data to include
>>> various x2 clock nodes between DPLL and HS dividers as the
>>> clock framework skips a x2 while calculating the dpll locked
>>> frequency.
>>>
>>> The clock database extensions are autogenerated using
>>> the scripts maintained by Benoit Cousson.
>>>
>>> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
>>> Signed-off-by: Thara Gopinath <thara@ti.com>
>>> [paul at pwsan.com: fixed merge conflicts against v2.6.37-rc5]
>>> Signed-off-by: Paul Walmsley <paul@pwsan.com>
>>> Cc: Rajendra Nayak <rnayak@ti.com>
>>
>>This patch has been updated to drop dpll_mpu_x2_ck. According to Beno?t
>>there is no need for this clock because there are no users of it, and the
>>script has been updated accordingly.
dpll_mpu_x2_ck was added to maintain the compatibility with other dpll
nodes. You can drop it if there is no use for it and you perceive no use
for it in OMAP4.
Regards
Thara
>>
>>
>>- Paul
>>
>>From: Thara Gopinath <thara@ti.com>
>>Date: Tue, 21 Dec 2010 18:11:05 -0700
>>Subject: [PATCH] OMAP4: clock data: Add missing DPLL x2 clock nodes
>>MIME-Version: 1.0
>>Content-Type: text/plain; charset=UTF-8
>>Content-Transfer-Encoding: 8bit
>>
>>This patch extends the OMAP4 clock data to include
>>various x2 clock nodes between DPLL and HS dividers as the
>>clock framework skips a x2 while calculating the dpll locked
>>frequency.
>>
>>The clock database extensions are autogenerated using
>>the scripts maintained by Benoit Cousson.
>>
>>Signed-off-by: Benoit Cousson <b-cousson@ti.com>
>>Signed-off-by: Thara Gopinath <thara@ti.com>
>>[paul at pwsan.com: fixed merge conflicts against v2.6.37-rc5; dropped
>> dpll_mpu_x2_ck on advice from Beno?t]
>>Signed-off-by: Paul Walmsley <paul@pwsan.com>
>>Cc: Rajendra Nayak <rnayak@ti.com>
>>---
>> arch/arm/mach-omap2/clock44xx_data.c | 415 ++++++++++++++++++++---------
>>-----
>> 1 files changed, 240 insertions(+), 175 deletions(-)
>>
>>diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-
>>omap2/clock44xx_data.c
>>index 305019c4..7c8d7f4 100644
>>--- a/arch/arm/mach-omap2/clock44xx_data.c
>>+++ b/arch/arm/mach-omap2/clock44xx_data.c
>>@@ -275,11 +275,63 @@ static struct clk dpll_abe_ck = {
>> .set_rate = &omap3_noncore_dpll_set_rate,
>> };
>>
>>+static struct clk dpll_abe_x2_ck = {
>>+ .name = "dpll_abe_x2_ck",
>>+ .parent = &dpll_abe_ck,
>>+ .ops = &clkops_null,
>>+ .recalc = &omap3_clkoutx2_recalc,
>>+};
>>+
>>+static const struct clksel_rate div31_1to31_rates[] = {
>>+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
>>+ { .div = 2, .val = 2, .flags = RATE_IN_4430 },
>>+ { .div = 3, .val = 3, .flags = RATE_IN_4430 },
>>+ { .div = 4, .val = 4, .flags = RATE_IN_4430 },
>>+ { .div = 5, .val = 5, .flags = RATE_IN_4430 },
>>+ { .div = 6, .val = 6, .flags = RATE_IN_4430 },
>>+ { .div = 7, .val = 7, .flags = RATE_IN_4430 },
>>+ { .div = 8, .val = 8, .flags = RATE_IN_4430 },
>>+ { .div = 9, .val = 9, .flags = RATE_IN_4430 },
>>+ { .div = 10, .val = 10, .flags = RATE_IN_4430 },
>>+ { .div = 11, .val = 11, .flags = RATE_IN_4430 },
>>+ { .div = 12, .val = 12, .flags = RATE_IN_4430 },
>>+ { .div = 13, .val = 13, .flags = RATE_IN_4430 },
>>+ { .div = 14, .val = 14, .flags = RATE_IN_4430 },
>>+ { .div = 15, .val = 15, .flags = RATE_IN_4430 },
>>+ { .div = 16, .val = 16, .flags = RATE_IN_4430 },
>>+ { .div = 17, .val = 17, .flags = RATE_IN_4430 },
>>+ { .div = 18, .val = 18, .flags = RATE_IN_4430 },
>>+ { .div = 19, .val = 19, .flags = RATE_IN_4430 },
>>+ { .div = 20, .val = 20, .flags = RATE_IN_4430 },
>>+ { .div = 21, .val = 21, .flags = RATE_IN_4430 },
>>+ { .div = 22, .val = 22, .flags = RATE_IN_4430 },
>>+ { .div = 23, .val = 23, .flags = RATE_IN_4430 },
>>+ { .div = 24, .val = 24, .flags = RATE_IN_4430 },
>>+ { .div = 25, .val = 25, .flags = RATE_IN_4430 },
>>+ { .div = 26, .val = 26, .flags = RATE_IN_4430 },
>>+ { .div = 27, .val = 27, .flags = RATE_IN_4430 },
>>+ { .div = 28, .val = 28, .flags = RATE_IN_4430 },
>>+ { .div = 29, .val = 29, .flags = RATE_IN_4430 },
>>+ { .div = 30, .val = 30, .flags = RATE_IN_4430 },
>>+ { .div = 31, .val = 31, .flags = RATE_IN_4430 },
>>+ { .div = 0 },
>>+};
>>+
>>+static const struct clksel dpll_abe_m2x2_div[] = {
>>+ { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
>>+ { .parent = NULL },
>>+};
>>+
>> static struct clk dpll_abe_m2x2_ck = {
>> .name = "dpll_abe_m2x2_ck",
>>- .parent = &dpll_abe_ck,
>>+ .parent = &dpll_abe_x2_ck,
>>+ .clksel = dpll_abe_m2x2_div,
>>+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
>>+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
>> .ops = &clkops_null,
>>- .recalc = &followparent_recalc,
>>+ .recalc = &omap2_clksel_recalc,
>>+ .round_rate = &omap2_clksel_round_rate,
>>+ .set_rate = &omap2_clksel_set_rate,
>> };
>>
>> static struct clk abe_24m_fclk = {
>>@@ -336,50 +388,10 @@ static struct clk aess_fclk = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static const struct clksel_rate div31_1to31_rates[] = {
>>- { .div = 1, .val = 1, .flags = RATE_IN_4430 },
>>- { .div = 2, .val = 2, .flags = RATE_IN_4430 },
>>- { .div = 3, .val = 3, .flags = RATE_IN_4430 },
>>- { .div = 4, .val = 4, .flags = RATE_IN_4430 },
>>- { .div = 5, .val = 5, .flags = RATE_IN_4430 },
>>- { .div = 6, .val = 6, .flags = RATE_IN_4430 },
>>- { .div = 7, .val = 7, .flags = RATE_IN_4430 },
>>- { .div = 8, .val = 8, .flags = RATE_IN_4430 },
>>- { .div = 9, .val = 9, .flags = RATE_IN_4430 },
>>- { .div = 10, .val = 10, .flags = RATE_IN_4430 },
>>- { .div = 11, .val = 11, .flags = RATE_IN_4430 },
>>- { .div = 12, .val = 12, .flags = RATE_IN_4430 },
>>- { .div = 13, .val = 13, .flags = RATE_IN_4430 },
>>- { .div = 14, .val = 14, .flags = RATE_IN_4430 },
>>- { .div = 15, .val = 15, .flags = RATE_IN_4430 },
>>- { .div = 16, .val = 16, .flags = RATE_IN_4430 },
>>- { .div = 17, .val = 17, .flags = RATE_IN_4430 },
>>- { .div = 18, .val = 18, .flags = RATE_IN_4430 },
>>- { .div = 19, .val = 19, .flags = RATE_IN_4430 },
>>- { .div = 20, .val = 20, .flags = RATE_IN_4430 },
>>- { .div = 21, .val = 21, .flags = RATE_IN_4430 },
>>- { .div = 22, .val = 22, .flags = RATE_IN_4430 },
>>- { .div = 23, .val = 23, .flags = RATE_IN_4430 },
>>- { .div = 24, .val = 24, .flags = RATE_IN_4430 },
>>- { .div = 25, .val = 25, .flags = RATE_IN_4430 },
>>- { .div = 26, .val = 26, .flags = RATE_IN_4430 },
>>- { .div = 27, .val = 27, .flags = RATE_IN_4430 },
>>- { .div = 28, .val = 28, .flags = RATE_IN_4430 },
>>- { .div = 29, .val = 29, .flags = RATE_IN_4430 },
>>- { .div = 30, .val = 30, .flags = RATE_IN_4430 },
>>- { .div = 31, .val = 31, .flags = RATE_IN_4430 },
>>- { .div = 0 },
>>-};
>>-
>>-static const struct clksel dpll_abe_m3_div[] = {
>>- { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
>>- { .parent = NULL },
>>-};
>>-
>>-static struct clk dpll_abe_m3_ck = {
>>- .name = "dpll_abe_m3_ck",
>>- .parent = &dpll_abe_ck,
>>- .clksel = dpll_abe_m3_div,
>>+static struct clk dpll_abe_m3x2_ck = {
>>+ .name = "dpll_abe_m3x2_ck",
>>+ .parent = &dpll_abe_x2_ck,
>>+ .clksel = dpll_abe_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
>> .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -390,7 +402,7 @@ static struct clk dpll_abe_m3_ck = {
>>
>> static const struct clksel core_hsd_byp_clk_mux_sel[] = {
>> { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
>>- { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
>>+ { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
>> { .parent = NULL },
>> };
>>
>>@@ -434,15 +446,22 @@ static struct clk dpll_core_ck = {
>> .recalc = &omap3_dpll_recalc,
>> };
>>
>>-static const struct clksel dpll_core_m6_div[] = {
>>- { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
>>+static struct clk dpll_core_x2_ck = {
>>+ .name = "dpll_core_x2_ck",
>>+ .parent = &dpll_core_ck,
>>+ .ops = &clkops_null,
>>+ .recalc = &omap3_clkoutx2_recalc,
>>+};
>>+
>>+static const struct clksel dpll_core_m6x2_div[] = {
>>+ { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
>> { .parent = NULL },
>> };
>>
>>-static struct clk dpll_core_m6_ck = {
>>- .name = "dpll_core_m6_ck",
>>- .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+static struct clk dpll_core_m6x2_ck = {
>>+ .name = "dpll_core_m6x2_ck",
>>+ .parent = &dpll_core_x2_ck,
>>+ .clksel = dpll_core_m6x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -453,7 +472,7 @@ static struct clk dpll_core_m6_ck = {
>>
>> static const struct clksel dbgclk_mux_sel[] = {
>> { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
>>- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
>>+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
>> { .parent = NULL },
>> };
>>
>>@@ -464,10 +483,15 @@ static struct clk dbgclk_mux_ck = {
>> .recalc = &followparent_recalc,
>> };
>>
>>+static const struct clksel dpll_core_m2_div[] = {
>>+ { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
>>+ { .parent = NULL },
>>+};
>>+
>> static struct clk dpll_core_m2_ck = {
>> .name = "dpll_core_m2_ck",
>> .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+ .clksel = dpll_core_m2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
>> .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -483,10 +507,10 @@ static struct clk ddrphy_ck = {
>> .recalc = &followparent_recalc,
>> };
>>
>>-static struct clk dpll_core_m5_ck = {
>>- .name = "dpll_core_m5_ck",
>>- .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+static struct clk dpll_core_m5x2_ck = {
>>+ .name = "dpll_core_m5x2_ck",
>>+ .parent = &dpll_core_x2_ck,
>>+ .clksel = dpll_core_m6x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -496,13 +520,13 @@ static struct clk dpll_core_m5_ck = {
>> };
>>
>> static const struct clksel div_core_div[] = {
>>- { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
>>+ { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
>> { .parent = NULL },
>> };
>>
>> static struct clk div_core_ck = {
>> .name = "div_core_ck",
>>- .parent = &dpll_core_m5_ck,
>>+ .parent = &dpll_core_m5x2_ck,
>> .clksel = div_core_div,
>> .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
>> .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
>>@@ -521,13 +545,13 @@ static const struct clksel_rate div4_1to8_rates[] =
>>{
>> };
>>
>> static const struct clksel div_iva_hs_clk_div[] = {
>>- { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
>>+ { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
>> { .parent = NULL },
>> };
>>
>> static struct clk div_iva_hs_clk = {
>> .name = "div_iva_hs_clk",
>>- .parent = &dpll_core_m5_ck,
>>+ .parent = &dpll_core_m5x2_ck,
>> .clksel = div_iva_hs_clk_div,
>> .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
>> .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
>>@@ -539,7 +563,7 @@ static struct clk div_iva_hs_clk = {
>>
>> static struct clk div_mpu_hs_clk = {
>> .name = "div_mpu_hs_clk",
>>- .parent = &dpll_core_m5_ck,
>>+ .parent = &dpll_core_m5x2_ck,
>> .clksel = div_iva_hs_clk_div,
>> .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
>> .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
>>@@ -549,10 +573,10 @@ static struct clk div_mpu_hs_clk = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_core_m4_ck = {
>>- .name = "dpll_core_m4_ck",
>>- .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+static struct clk dpll_core_m4x2_ck = {
>>+ .name = "dpll_core_m4x2_ck",
>>+ .parent = &dpll_core_x2_ck,
>>+ .clksel = dpll_core_m6x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -563,15 +587,20 @@ static struct clk dpll_core_m4_ck = {
>>
>> static struct clk dll_clk_div_ck = {
>> .name = "dll_clk_div_ck",
>>- .parent = &dpll_core_m4_ck,
>>+ .parent = &dpll_core_m4x2_ck,
>> .ops = &clkops_null,
>> .recalc = &followparent_recalc,
>> };
>>
>>+static const struct clksel dpll_abe_m2_div[] = {
>>+ { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
>>+ { .parent = NULL },
>>+};
>>+
>> static struct clk dpll_abe_m2_ck = {
>> .name = "dpll_abe_m2_ck",
>> .parent = &dpll_abe_ck,
>>- .clksel = dpll_abe_m3_div,
>>+ .clksel = dpll_abe_m2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
>> .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -580,10 +609,10 @@ static struct clk dpll_abe_m2_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_core_m3_ck = {
>>- .name = "dpll_core_m3_ck",
>>- .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+static struct clk dpll_core_m3x2_ck = {
>>+ .name = "dpll_core_m3x2_ck",
>>+ .parent = &dpll_core_x2_ck,
>>+ .clksel = dpll_core_m6x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
>> .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -592,10 +621,10 @@ static struct clk dpll_core_m3_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_core_m7_ck = {
>>- .name = "dpll_core_m7_ck",
>>- .parent = &dpll_core_ck,
>>- .clksel = dpll_core_m6_div,
>>+static struct clk dpll_core_m7x2_ck = {
>>+ .name = "dpll_core_m7x2_ck",
>>+ .parent = &dpll_core_x2_ck,
>>+ .clksel = dpll_core_m6x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -648,15 +677,22 @@ static struct clk dpll_iva_ck = {
>> .set_rate = &omap3_noncore_dpll_set_rate,
>> };
>>
>>-static const struct clksel dpll_iva_m4_div[] = {
>>- { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
>>+static struct clk dpll_iva_x2_ck = {
>>+ .name = "dpll_iva_x2_ck",
>>+ .parent = &dpll_iva_ck,
>>+ .ops = &clkops_null,
>>+ .recalc = &omap3_clkoutx2_recalc,
>>+};
>>+
>>+static const struct clksel dpll_iva_m4x2_div[] = {
>>+ { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
>> { .parent = NULL },
>> };
>>
>>-static struct clk dpll_iva_m4_ck = {
>>- .name = "dpll_iva_m4_ck",
>>- .parent = &dpll_iva_ck,
>>- .clksel = dpll_iva_m4_div,
>>+static struct clk dpll_iva_m4x2_ck = {
>>+ .name = "dpll_iva_m4x2_ck",
>>+ .parent = &dpll_iva_x2_ck,
>>+ .clksel = dpll_iva_m4x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -665,10 +701,10 @@ static struct clk dpll_iva_m4_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_iva_m5_ck = {
>>- .name = "dpll_iva_m5_ck",
>>- .parent = &dpll_iva_ck,
>>- .clksel = dpll_iva_m4_div,
>>+static struct clk dpll_iva_m5x2_ck = {
>>+ .name = "dpll_iva_m5x2_ck",
>>+ .parent = &dpll_iva_x2_ck,
>>+ .clksel = dpll_iva_m4x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -727,7 +763,7 @@ static struct clk dpll_mpu_m2_ck = {
>>
>> static struct clk per_hs_clk_div_ck = {
>> .name = "per_hs_clk_div_ck",
>>- .parent = &dpll_abe_m3_ck,
>>+ .parent = &dpll_abe_m3x2_ck,
>> .ops = &clkops_null,
>> .recalc = &followparent_recalc,
>> };
>>@@ -797,17 +833,34 @@ static struct clk dpll_per_m2_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>+static struct clk dpll_per_x2_ck = {
>>+ .name = "dpll_per_x2_ck",
>>+ .parent = &dpll_per_ck,
>>+ .ops = &clkops_null,
>>+ .recalc = &omap3_clkoutx2_recalc,
>>+};
>>+
>>+static const struct clksel dpll_per_m2x2_div[] = {
>>+ { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
>>+ { .parent = NULL },
>>+};
>>+
>> static struct clk dpll_per_m2x2_ck = {
>> .name = "dpll_per_m2x2_ck",
>>- .parent = &dpll_per_ck,
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>>+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
>>+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
>> .ops = &clkops_null,
>>- .recalc = &followparent_recalc,
>>+ .recalc = &omap2_clksel_recalc,
>>+ .round_rate = &omap2_clksel_round_rate,
>>+ .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_per_m3_ck = {
>>- .name = "dpll_per_m3_ck",
>>- .parent = &dpll_per_ck,
>>- .clksel = dpll_per_m2_div,
>>+static struct clk dpll_per_m3x2_ck = {
>>+ .name = "dpll_per_m3x2_ck",
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
>> .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -816,10 +869,10 @@ static struct clk dpll_per_m3_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_per_m4_ck = {
>>- .name = "dpll_per_m4_ck",
>>- .parent = &dpll_per_ck,
>>- .clksel = dpll_per_m2_div,
>>+static struct clk dpll_per_m4x2_ck = {
>>+ .name = "dpll_per_m4x2_ck",
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -828,10 +881,10 @@ static struct clk dpll_per_m4_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_per_m5_ck = {
>>- .name = "dpll_per_m5_ck",
>>- .parent = &dpll_per_ck,
>>- .clksel = dpll_per_m2_div,
>>+static struct clk dpll_per_m5x2_ck = {
>>+ .name = "dpll_per_m5x2_ck",
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -840,10 +893,10 @@ static struct clk dpll_per_m5_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_per_m6_ck = {
>>- .name = "dpll_per_m6_ck",
>>- .parent = &dpll_per_ck,
>>- .clksel = dpll_per_m2_div,
>>+static struct clk dpll_per_m6x2_ck = {
>>+ .name = "dpll_per_m6x2_ck",
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -852,10 +905,10 @@ static struct clk dpll_per_m6_ck = {
>> .set_rate = &omap2_clksel_set_rate,
>> };
>>
>>-static struct clk dpll_per_m7_ck = {
>>- .name = "dpll_per_m7_ck",
>>- .parent = &dpll_per_ck,
>>- .clksel = dpll_per_m2_div,
>>+static struct clk dpll_per_m7x2_ck = {
>>+ .name = "dpll_per_m7x2_ck",
>>+ .parent = &dpll_per_x2_ck,
>>+ .clksel = dpll_per_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
>> .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
>> .ops = &clkops_null,
>>@@ -895,14 +948,21 @@ static struct clk dpll_unipro_ck = {
>> .set_rate = &omap3_noncore_dpll_set_rate,
>> };
>>
>>+static struct clk dpll_unipro_x2_ck = {
>>+ .name = "dpll_unipro_x2_ck",
>>+ .parent = &dpll_unipro_ck,
>>+ .ops = &clkops_null,
>>+ .recalc = &omap3_clkoutx2_recalc,
>>+};
>>+
>> static const struct clksel dpll_unipro_m2x2_div[] = {
>>- { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
>>+ { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
>> { .parent = NULL },
>> };
>>
>> static struct clk dpll_unipro_m2x2_ck = {
>> .name = "dpll_unipro_m2x2_ck",
>>- .parent = &dpll_unipro_ck,
>>+ .parent = &dpll_unipro_x2_ck,
>> .clksel = dpll_unipro_m2x2_div,
>> .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
>> .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
>>@@ -914,7 +974,7 @@ static struct clk dpll_unipro_m2x2_ck = {
>>
>> static struct clk usb_hs_clk_div_ck = {
>> .name = "usb_hs_clk_div_ck",
>>- .parent = &dpll_abe_m3_ck,
>>+ .parent = &dpll_abe_m3x2_ck,
>> .ops = &clkops_null,
>> .recalc = &followparent_recalc,
>> };
>>@@ -977,7 +1037,7 @@ static struct clk dpll_usb_m2_ck = {
>>
>> static const struct clksel ducati_clk_mux_sel[] = {
>> { .parent = &div_core_ck, .rates = div_1_0_rates },
>>- { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
>>+ { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
>> { .parent = NULL },
>> };
>>
>>@@ -1050,13 +1110,13 @@ static const struct clksel_rate div2_2to4_rates[]
>>= {
>> };
>>
>> static const struct clksel func_64m_fclk_div[] = {
>>- { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
>>+ { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
>> { .parent = NULL },
>> };
>>
>> static struct clk func_64m_fclk = {
>> .name = "func_64m_fclk",
>>- .parent = &dpll_per_m4_ck,
>>+ .parent = &dpll_per_m4x2_ck,
>> .clksel = func_64m_fclk_div,
>> .clksel_reg = OMAP4430_CM_SCALE_FCLK,
>> .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
>>@@ -1230,7 +1290,7 @@ static struct clk per_abe_24m_fclk = {
>>
>> static const struct clksel pmd_stm_clock_mux_sel[] = {
>> { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
>>- { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
>>+ { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
>> { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
>> { .parent = NULL },
>> };
>>@@ -1364,7 +1424,7 @@ static struct clk dsp_fck = {
>> .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
>> .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
>> .clkdm_name = "tesla_clkdm",
>>- .parent = &dpll_iva_m4_ck,
>>+ .parent = &dpll_iva_m4x2_ck,
>> .recalc = &followparent_recalc,
>> };
>>
>>@@ -1394,7 +1454,7 @@ static struct clk dss_dss_clk = {
>> .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
>> .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
>> .clkdm_name = "l3_dss_clkdm",
>>- .parent = &dpll_per_m5_ck,
>>+ .parent = &dpll_per_m5x2_ck,
>> .recalc = &followparent_recalc,
>> };
>>
>>@@ -1451,14 +1511,14 @@ static struct clk emif2_fck = {
>> };
>>
>> static const struct clksel fdif_fclk_div[] = {
>>- { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
>>+ { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
>> { .parent = NULL },
>> };
>>
>> /* Merged fdif_fclk into fdif */
>> static struct clk fdif_fck = {
>> .name = "fdif_fck",
>>- .parent = &dpll_per_m4_ck,
>>+ .parent = &dpll_per_m4x2_ck,
>> .clksel = fdif_fclk_div,
>> .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
>> .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
>>@@ -1612,15 +1672,15 @@ static struct clk gpmc_ick = {
>> };
>>
>> static const struct clksel sgx_clk_mux_sel[] = {
>>- { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
>>- { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
>>+ { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
>>+ { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
>> { .parent = NULL },
>> };
>>
>> /* Merged sgx_clk_mux into gpu */
>> static struct clk gpu_fck = {
>> .name = "gpu_fck",
>>- .parent = &dpll_core_m7_ck,
>>+ .parent = &dpll_core_m7x2_ck,
>> .clksel = sgx_clk_mux_sel,
>> .init = &omap2_init_clksel_parent,
>> .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
>>@@ -1739,7 +1799,7 @@ static struct clk iva_fck = {
>> .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
>> .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
>> .clkdm_name = "ivahd_clkdm",
>>- .parent = &dpll_iva_m5_ck,
>>+ .parent = &dpll_iva_m5x2_ck,
>> .recalc = &followparent_recalc,
>> };
>>
>>@@ -2103,7 +2163,7 @@ static struct clk sl2if_ick = {
>> .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
>> .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
>> .clkdm_name = "ivahd_clkdm",
>>- .parent = &dpll_iva_m5_ck,
>>+ .parent = &dpll_iva_m5x2_ck,
>> .recalc = &followparent_recalc,
>> };
>>
>>@@ -2448,36 +2508,6 @@ static struct clk usb_host_fs_fck = {
>> .recalc = &followparent_recalc,
>> };
>>
>>-static struct clk usb_host_hs_utmi_p3_clk = {
>>- .name = "usb_host_hs_utmi_p3_clk",
>>- .ops = &clkops_omap2_dflt,
>>- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>- .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
>>- .clkdm_name = "l3_init_clkdm",
>>- .parent = &init_60m_fclk,
>>- .recalc = &followparent_recalc,
>>-};
>>-
>>-static struct clk usb_host_hs_hsic60m_p1_clk = {
>>- .name = "usb_host_hs_hsic60m_p1_clk",
>>- .ops = &clkops_omap2_dflt,
>>- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
>>- .clkdm_name = "l3_init_clkdm",
>>- .parent = &init_60m_fclk,
>>- .recalc = &followparent_recalc,
>>-};
>>-
>>-static struct clk usb_host_hs_hsic60m_p2_clk = {
>>- .name = "usb_host_hs_hsic60m_p2_clk",
>>- .ops = &clkops_omap2_dflt,
>>- .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>- .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
>>- .clkdm_name = "l3_init_clkdm",
>>- .parent = &init_60m_fclk,
>>- .recalc = &followparent_recalc,
>>-};
>>-
>> static const struct clksel utmi_p1_gfclk_sel[] = {
>> { .parent = &init_60m_fclk, .rates = div_1_0_rates },
>> { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
>>@@ -2532,6 +2562,16 @@ static struct clk usb_host_hs_utmi_p2_clk = {
>> .recalc = &followparent_recalc,
>> };
>>
>>+static struct clk usb_host_hs_utmi_p3_clk = {
>>+ .name = "usb_host_hs_utmi_p3_clk",
>>+ .ops = &clkops_omap2_dflt,
>>+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>+ .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
>>+ .clkdm_name = "l3_init_clkdm",
>>+ .parent = &init_60m_fclk,
>>+ .recalc = &followparent_recalc,
>>+};
>>+
>> static struct clk usb_host_hs_hsic480m_p1_clk = {
>> .name = "usb_host_hs_hsic480m_p1_clk",
>> .ops = &clkops_omap2_dflt,
>>@@ -2542,6 +2582,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
>> .recalc = &followparent_recalc,
>> };
>>
>>+static struct clk usb_host_hs_hsic60m_p1_clk = {
>>+ .name = "usb_host_hs_hsic60m_p1_clk",
>>+ .ops = &clkops_omap2_dflt,
>>+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
>>+ .clkdm_name = "l3_init_clkdm",
>>+ .parent = &init_60m_fclk,
>>+ .recalc = &followparent_recalc,
>>+};
>>+
>>+static struct clk usb_host_hs_hsic60m_p2_clk = {
>>+ .name = "usb_host_hs_hsic60m_p2_clk",
>>+ .ops = &clkops_omap2_dflt,
>>+ .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
>>+ .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
>>+ .clkdm_name = "l3_init_clkdm",
>>+ .parent = &init_60m_fclk,
>>+ .recalc = &followparent_recalc,
>>+};
>>+
>> static struct clk usb_host_hs_hsic480m_p2_clk = {
>> .name = "usb_host_hs_hsic480m_p2_clk",
>> .ops = &clkops_omap2_dflt,
>>@@ -2666,13 +2726,13 @@ static const struct clksel_rate
>>div2_14to18_rates[] = {
>> };
>>
>> static const struct clksel usim_fclk_div[] = {
>>- { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
>>+ { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
>> { .parent = NULL },
>> };
>>
>> static struct clk usim_ck = {
>> .name = "usim_ck",
>>- .parent = &dpll_per_m4_ck,
>>+ .parent = &dpll_per_m4x2_ck,
>> .clksel = usim_fclk_div,
>> .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
>> .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
>>@@ -2784,43 +2844,48 @@ static struct omap_clk omap44xx_clks[] = {
>> CLK(NULL, "abe_dpll_bypass_clk_mux_ck",
>> &abe_dpll_bypass_clk_mux_ck, CK_443X),
>> CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck,
>> CK_443X),
>> CLK(NULL, "dpll_abe_ck", &dpll_abe_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
>> CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
>> CK_443X),
>> CLK(NULL, "abe_24m_fclk", &abe_24m_fclk,
>> CK_443X),
>> CLK(NULL, "abe_clk", &abe_clk, CK_443X),
>> CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
>>- CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
>>+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck,
>> CK_443X),
>> CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck,
>> CK_443X),
>> CLK(NULL, "dpll_core_ck", &dpll_core_ck,
>> CK_443X),
>>- CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck,
>> CK_443X),
>> CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
>> CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck,
>> CK_443X),
>> CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
>>- CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
>> CK_443X),
>> CLK(NULL, "div_core_ck", &div_core_ck,
>> CK_443X),
>> CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
>> CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
>>- CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
>> CK_443X),
>> CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
>> CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
>>- CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck,
>> CK_443X),
>>- CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck,
>> CK_443X),
>> CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck,
>> CK_443X),
>> CLK(NULL, "dpll_iva_ck", &dpll_iva_ck,
>> CK_443X),
>>- CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
>>- CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
>>+ CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
>>+ CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck,
>> CK_443X),
>> CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck,
>> CK_443X),
>> CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
>> CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck,
>> CK_443X),
>> CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck,
>> CK_443X),
>> CLK(NULL, "dpll_per_ck", &dpll_per_ck,
>> CK_443X),
>> CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
>>+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
>> CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
>> CK_443X),
>>- CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
>>- CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
>>- CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
>>- CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
>>- CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
>>+ CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck,
>> CK_443X),
>>+ CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck,
>> CK_443X),
>> CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
>>+ CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck,
>> CK_443X),
>> CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck,
>> CK_443X),
>> CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck,
>> CK_443X),
>> CLK(NULL, "dpll_usb_ck", &dpll_usb_ck,
>> CK_443X),
>>@@ -2947,14 +3012,14 @@ static struct omap_clk omap44xx_clks[] = {
>> CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
>> CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
>> CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck,
>> CK_443X),
>>- CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk,
>> CK_443X),
>>- CLK(NULL, "usb_host_hs_hsic60m_p1_clk",
>> &usb_host_hs_hsic60m_p1_clk, CK_443X),
>>- CLK(NULL, "usb_host_hs_hsic60m_p2_clk",
>> &usb_host_hs_hsic60m_p2_clk, CK_443X),
>> CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
>> CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk,
>> CK_443X),
>> CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
>> CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk,
>> CK_443X),
>>+ CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk,
>> CK_443X),
>> CLK(NULL, "usb_host_hs_hsic480m_p1_clk",
>> &usb_host_hs_hsic480m_p1_clk, CK_443X),
>>+ CLK(NULL, "usb_host_hs_hsic60m_p1_clk",
>> &usb_host_hs_hsic60m_p1_clk, CK_443X),
>>+ CLK(NULL, "usb_host_hs_hsic60m_p2_clk",
>> &usb_host_hs_hsic60m_p2_clk, CK_443X),
>> CLK(NULL, "usb_host_hs_hsic480m_p2_clk",
>> &usb_host_hs_hsic480m_p2_clk, CK_443X),
>> CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk,
>> CK_443X),
>> CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck,
>> CK_443X),
>>--
>>1.7.2.3
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 04/12] OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ck
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (2 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 03/12] OMAP4: clock data: Add missing DPLL x2 clock nodes Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 05/12] OMAP4: PRCM: Add SCRM header file Paul Walmsley
` (9 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Jonathan Bergsagel <jbergsagel@ti.com>
Add register address, mask and link to the clksel structure that
were missing in the IVA DPLL mux clock node.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index aa503cb..421103c 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -636,8 +636,12 @@ static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
static struct clk iva_hsd_byp_clk_mux_ck = {
.name = "iva_hsd_byp_clk_mux_ck",
.parent = &sys_clkin_ck,
+ .clksel = iva_hsd_byp_clk_mux_sel,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
+ .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
};
/* DPLL_IVA */
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (3 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 04/12] OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ck Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 13:59 ` Cousson, Benoit
2010-12-15 1:17 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 06/12] OMAP4: clock data: Add SCRM auxiliary clock nodes Paul Walmsley
` (8 subsequent siblings)
13 siblings, 2 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Benoit Cousson <b-cousson@ti.com>
Add the header file with scrm registers absolute address, offset
and bitfields.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/scrm44xx.h | 176 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/scrm44xx.h
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
new file mode 100644
index 0000000..d29bf27
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -0,0 +1,176 @@
+/*
+ * OMAP44xx SCRM registers and bitfields
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap at vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+
+/* Base address */
+#define OMAP4_SCRM 0x4a30a000
+
+#define OMAP44XX_SCRM_REGADDR(reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP4_SCRM + (reg))
+
+/* Registers offset */
+#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000
+#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000)
+#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100
+#define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100)
+#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104
+#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104)
+#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110
+#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110)
+#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118
+#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118)
+#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c
+#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c)
+#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200
+#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200)
+#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204
+#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204)
+#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208
+#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208)
+#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210
+#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210)
+#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214
+#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214)
+#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218
+#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218)
+#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c
+#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c)
+#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220
+#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220)
+#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224
+#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224)
+#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234
+#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234)
+#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310
+#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310)
+#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314
+#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314)
+#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318
+#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318)
+#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c
+#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c)
+#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320
+#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320)
+#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324
+#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324)
+#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400
+#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400)
+#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418
+#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418)
+#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c
+#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c)
+#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
+#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420)
+#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510
+#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510)
+#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514
+#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514)
+#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518
+#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518)
+#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c
+#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c)
+
+/* Registers shifts and masks */
+
+/* REVISION_SCRM */
+#define OMAP4_REV_SHIFT 0
+#define OMAP4_REV_MASK (0xff << 0)
+
+/* CLKSETUPTIME */
+#define OMAP4_DOWNTIME_SHIFT 16
+#define OMAP4_DOWNTIME_MASK (0x3f << 16)
+#define OMAP4_SETUPTIME_SHIFT 0
+#define OMAP4_SETUPTIME_MASK (0xfff << 0)
+
+/* PMICSETUPTIME */
+#define OMAP4_WAKEUPTIME_SHIFT 16
+#define OMAP4_WAKEUPTIME_MASK (0x3f << 16)
+#define OMAP4_SLEEPTIME_SHIFT 0
+#define OMAP4_SLEEPTIME_MASK (0x3f << 0)
+
+/* ALTCLKSRC */
+#define OMAP4_ENABLE_EXT_SHIFT 3
+#define OMAP4_ENABLE_EXT_MASK (1 << 3)
+#define OMAP4_ENABLE_INT_SHIFT 2
+#define OMAP4_ENABLE_INT_MASK (1 << 2)
+#define OMAP4_ALTCLKSRC_MODE_SHIFT 0
+#define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0)
+
+/* MODEMCLKM */
+#define OMAP4_CLK_32KHZ_SHIFT 0
+#define OMAP4_CLK_32KHZ_MASK (1 << 0)
+
+/* D2DCLKM */
+#define OMAP4_SYSCLK_SHIFT 1
+#define OMAP4_SYSCLK_MASK (1 << 1)
+
+/* EXTCLKREQ */
+#define OMAP4_POLARITY_SHIFT 0
+#define OMAP4_POLARITY_MASK (1 << 0)
+
+/* AUXCLKREQ0 */
+#define OMAP4_MAPPING_SHIFT 2
+#define OMAP4_MAPPING_MASK (0x7 << 2)
+#define OMAP4_ACCURACY_SHIFT 1
+#define OMAP4_ACCURACY_MASK (1 << 1)
+
+/* AUXCLK0 */
+#define OMAP4_CLKDIV_SHIFT 16
+#define OMAP4_CLKDIV_MASK (0xf << 16)
+#define OMAP4_DISABLECLK_SHIFT 9
+#define OMAP4_DISABLECLK_MASK (1 << 9)
+#define OMAP4_ENABLE_SHIFT 8
+#define OMAP4_ENABLE_MASK (1 << 8)
+#define OMAP4_SRCSELECT_SHIFT 1
+#define OMAP4_SRCSELECT_MASK (0x3 << 1)
+
+/* RSTTIME */
+#define OMAP4_RSTTIME_SHIFT 0
+#define OMAP4_RSTTIME_MASK (0xf << 0)
+
+/* MODEMRSTCTRL */
+#define OMAP4_WARMRST_SHIFT 1
+#define OMAP4_WARMRST_MASK (1 << 1)
+#define OMAP4_COLDRST_SHIFT 0
+#define OMAP4_COLDRST_MASK (1 << 0)
+
+/* EXTPWRONRSTCTRL */
+#define OMAP4_PWRONRST_SHIFT 1
+#define OMAP4_PWRONRST_MASK (1 << 1)
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0)
+
+/* EXTWARMRSTST */
+#define OMAP4_EXTWARMRSTST_SHIFT 0
+#define OMAP4_EXTWARMRSTST_MASK (1 << 0)
+
+/* APEWARMRSTST */
+#define OMAP4_APEWARMRSTST_SHIFT 1
+#define OMAP4_APEWARMRSTST_MASK (1 << 1)
+
+/* MODEMWARMRSTST */
+#define OMAP4_MODEMWARMRSTST_SHIFT 2
+#define OMAP4_MODEMWARMRSTST_MASK (1 << 2)
+
+/* D2DWARMRSTST */
+#define OMAP4_D2DWARMRSTST_SHIFT 3
+#define OMAP4_D2DWARMRSTST_MASK (1 << 3)
+
+#endif
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 6:34 ` [PATCH 05/12] OMAP4: PRCM: Add SCRM header file Paul Walmsley
@ 2010-12-14 13:59 ` Cousson, Benoit
2010-12-14 18:13 ` Paul Walmsley
2010-12-15 1:17 ` Paul Walmsley
1 sibling, 1 reply; 24+ messages in thread
From: Cousson, Benoit @ 2010-12-14 13:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paul,
This patch will conflict with your power prcm series, because you are
creating an empty scrm44xx.h in it.
So I did rebased this series on top on your prcm to fix that.
Don't you want to use the already rebased version instead?
Regards,
Benoit
On 12/14/2010 7:34 AM, Paul Walmsley wrote:
> From: Benoit Cousson<b-cousson@ti.com>
>
> Add the header file with scrm registers absolute address, offset
> and bitfields.
>
> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
> Signed-off-by: Rajendra Nayak<rnayak@ti.com>
> Signed-off-by: Paul Walmsley<paul@pwsan.com>
> ---
> arch/arm/mach-omap2/scrm44xx.h | 176 ++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 176 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-omap2/scrm44xx.h
>
> diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
> new file mode 100644
> index 0000000..d29bf27
> --- /dev/null
> +++ b/arch/arm/mach-omap2/scrm44xx.h
> @@ -0,0 +1,176 @@
> +/*
> + * OMAP44xx SCRM registers and bitfields
> + *
> + * Copyright (C) 2010 Texas Instruments, Inc.
> + *
> + * Benoit Cousson (b-cousson at ti.com)
> + *
> + * This file is automatically generated from the OMAP hardware databases.
> + * We respectfully ask that any modifications to this file be coordinated
> + * with the public linux-omap at vger.kernel.org mailing list and the
> + * authors above to ensure that the autogeneration scripts are kept
> + * up-to-date with the file contents.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
> +#define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
> +
> +/* Base address */
> +#define OMAP4_SCRM 0x4a30a000
> +
> +#define OMAP44XX_SCRM_REGADDR(reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP4_SCRM + (reg))
> +
> +/* Registers offset */
> +#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000
> +#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000)
> +#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100
> +#define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100)
> +#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104
> +#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104)
> +#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110
> +#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110)
> +#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118
> +#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118)
> +#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c
> +#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c)
> +#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200
> +#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200)
> +#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204
> +#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204)
> +#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208
> +#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208)
> +#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210
> +#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210)
> +#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214
> +#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214)
> +#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218
> +#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218)
> +#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c
> +#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c)
> +#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220
> +#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220)
> +#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224
> +#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224)
> +#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234
> +#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234)
> +#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310
> +#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310)
> +#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314
> +#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314)
> +#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318
> +#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318)
> +#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c
> +#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c)
> +#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320
> +#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320)
> +#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324
> +#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324)
> +#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400
> +#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400)
> +#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418
> +#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418)
> +#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c
> +#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c)
> +#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
> +#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420)
> +#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510
> +#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510)
> +#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514
> +#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514)
> +#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518
> +#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518)
> +#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c
> +#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c)
> +
> +/* Registers shifts and masks */
> +
> +/* REVISION_SCRM */
> +#define OMAP4_REV_SHIFT 0
> +#define OMAP4_REV_MASK (0xff<< 0)
> +
> +/* CLKSETUPTIME */
> +#define OMAP4_DOWNTIME_SHIFT 16
> +#define OMAP4_DOWNTIME_MASK (0x3f<< 16)
> +#define OMAP4_SETUPTIME_SHIFT 0
> +#define OMAP4_SETUPTIME_MASK (0xfff<< 0)
> +
> +/* PMICSETUPTIME */
> +#define OMAP4_WAKEUPTIME_SHIFT 16
> +#define OMAP4_WAKEUPTIME_MASK (0x3f<< 16)
> +#define OMAP4_SLEEPTIME_SHIFT 0
> +#define OMAP4_SLEEPTIME_MASK (0x3f<< 0)
> +
> +/* ALTCLKSRC */
> +#define OMAP4_ENABLE_EXT_SHIFT 3
> +#define OMAP4_ENABLE_EXT_MASK (1<< 3)
> +#define OMAP4_ENABLE_INT_SHIFT 2
> +#define OMAP4_ENABLE_INT_MASK (1<< 2)
> +#define OMAP4_ALTCLKSRC_MODE_SHIFT 0
> +#define OMAP4_ALTCLKSRC_MODE_MASK (0x3<< 0)
> +
> +/* MODEMCLKM */
> +#define OMAP4_CLK_32KHZ_SHIFT 0
> +#define OMAP4_CLK_32KHZ_MASK (1<< 0)
> +
> +/* D2DCLKM */
> +#define OMAP4_SYSCLK_SHIFT 1
> +#define OMAP4_SYSCLK_MASK (1<< 1)
> +
> +/* EXTCLKREQ */
> +#define OMAP4_POLARITY_SHIFT 0
> +#define OMAP4_POLARITY_MASK (1<< 0)
> +
> +/* AUXCLKREQ0 */
> +#define OMAP4_MAPPING_SHIFT 2
> +#define OMAP4_MAPPING_MASK (0x7<< 2)
> +#define OMAP4_ACCURACY_SHIFT 1
> +#define OMAP4_ACCURACY_MASK (1<< 1)
> +
> +/* AUXCLK0 */
> +#define OMAP4_CLKDIV_SHIFT 16
> +#define OMAP4_CLKDIV_MASK (0xf<< 16)
> +#define OMAP4_DISABLECLK_SHIFT 9
> +#define OMAP4_DISABLECLK_MASK (1<< 9)
> +#define OMAP4_ENABLE_SHIFT 8
> +#define OMAP4_ENABLE_MASK (1<< 8)
> +#define OMAP4_SRCSELECT_SHIFT 1
> +#define OMAP4_SRCSELECT_MASK (0x3<< 1)
> +
> +/* RSTTIME */
> +#define OMAP4_RSTTIME_SHIFT 0
> +#define OMAP4_RSTTIME_MASK (0xf<< 0)
> +
> +/* MODEMRSTCTRL */
> +#define OMAP4_WARMRST_SHIFT 1
> +#define OMAP4_WARMRST_MASK (1<< 1)
> +#define OMAP4_COLDRST_SHIFT 0
> +#define OMAP4_COLDRST_MASK (1<< 0)
> +
> +/* EXTPWRONRSTCTRL */
> +#define OMAP4_PWRONRST_SHIFT 1
> +#define OMAP4_PWRONRST_MASK (1<< 1)
> +#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0
> +#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1<< 0)
> +
> +/* EXTWARMRSTST */
> +#define OMAP4_EXTWARMRSTST_SHIFT 0
> +#define OMAP4_EXTWARMRSTST_MASK (1<< 0)
> +
> +/* APEWARMRSTST */
> +#define OMAP4_APEWARMRSTST_SHIFT 1
> +#define OMAP4_APEWARMRSTST_MASK (1<< 1)
> +
> +/* MODEMWARMRSTST */
> +#define OMAP4_MODEMWARMRSTST_SHIFT 2
> +#define OMAP4_MODEMWARMRSTST_MASK (1<< 2)
> +
> +/* D2DWARMRSTST */
> +#define OMAP4_D2DWARMRSTST_SHIFT 3
> +#define OMAP4_D2DWARMRSTST_MASK (1<< 3)
> +
> +#endif
>
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 13:59 ` Cousson, Benoit
@ 2010-12-14 18:13 ` Paul Walmsley
2010-12-14 20:16 ` Cousson, Benoit
0 siblings, 1 reply; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 18:13 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 14 Dec 2010, Cousson, Benoit wrote:
> This patch will conflict with your power prcm series, because you are creating
> an empty scrm44xx.h in it.
>
> So I did rebased this series on top on your prcm to fix that.
>
> Don't you want to use the already rebased version instead?
I would rather have patches and branches based on mainline commits where
possible. If a series has some explicit dependency on a non-mainline
patch or branch then I'd like to know about it in the messages if
possible.
As far as the empty scrm44xx.h goes, I will probably go back and rebuild
that branch with your patch that creates SCRM from my patch set inserted
earlier, so I can drop the part of my patch that creates the empty file.
- Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 18:13 ` Paul Walmsley
@ 2010-12-14 20:16 ` Cousson, Benoit
2010-12-15 1:15 ` Paul Walmsley
0 siblings, 1 reply; 24+ messages in thread
From: Cousson, Benoit @ 2010-12-14 20:16 UTC (permalink / raw)
To: linux-arm-kernel
On 12/14/2010 7:13 PM, Paul Walmsley wrote:
> On Tue, 14 Dec 2010, Cousson, Benoit wrote:
>
>> This patch will conflict with your power prcm series, because you are creating
>> an empty scrm44xx.h in it.
>>
>> So I did rebased this series on top on your prcm to fix that.
>>
>> Don't you want to use the already rebased version instead?
>
> I would rather have patches and branches based on mainline commits where
> possible. If a series has some explicit dependency on a non-mainline
> patch or branch then I'd like to know about it in the messages if
> possible.
Well, I sent this series before you sent your prcm one, so at the time
the dependency didn't exist ;-)
> As far as the empty scrm44xx.h goes, I will probably go back and rebuild
> that branch with your patch that creates SCRM from my patch set inserted
> earlier, so I can drop the part of my patch that creates the empty file.
OK good for me.
Thanks,
Benoit
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 20:16 ` Cousson, Benoit
@ 2010-12-15 1:15 ` Paul Walmsley
0 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-15 1:15 UTC (permalink / raw)
To: linux-arm-kernel
Salut Beno?t
On Tue, 14 Dec 2010, Cousson, Benoit wrote:
> Well, I sent this series before you sent your prcm one, so at the time the
> dependency didn't exist ;-)
No worries, it was just meant to be a general suggestion, not a specific
one to this case.
> > As far as the empty scrm44xx.h goes, I will probably go back and rebuild
> > that branch with your patch that creates SCRM from my patch set inserted
> > earlier, so I can drop the part of my patch that creates the empty file.
I went ahead and moved the SCRM patch earlier in the branch sets. I did
make one change in it - I'll reply to it with the update details.
The current integration tag that contains the revised patch is
'integration-2.6.38-20101214-010' available from
git://git.pwsan.com/linux-integration
- Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/12] OMAP4: PRCM: Add SCRM header file
2010-12-14 6:34 ` [PATCH 05/12] OMAP4: PRCM: Add SCRM header file Paul Walmsley
2010-12-14 13:59 ` Cousson, Benoit
@ 2010-12-15 1:17 ` Paul Walmsley
1 sibling, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-15 1:17 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 13 Dec 2010, Paul Walmsley wrote:
> From: Benoit Cousson <b-cousson@ti.com>
>
> Add the header file with scrm registers absolute address, offset
> and bitfields.
>
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch has been moved to the earlier 'pwrdm_prcm_a_2.6.38' series.
Also the base address macro name has been changed from OMAP4_SCRM to
OMAP4_SCRM_BASE.
- Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 06/12] OMAP4: clock data: Add SCRM auxiliary clock nodes
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (4 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 05/12] OMAP4: PRCM: Add SCRM header file Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 07/12] OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocks Paul Walmsley
` (7 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Rajendra Nayak <rnayak@ti.com>
Add support for auxiliary clocks nodes which are part of SCRM.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 175 ++++++++++++++++++++++++++++++++++
1 files changed, 175 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 421103c..80a1898 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -35,6 +35,7 @@
#include "prm.h"
#include "prm-regbits-44xx.h"
#include "control.h"
+#include "scrm44xx.h"
/* Root clocks */
@@ -2822,6 +2823,168 @@ static struct clk trace_clk_div_ck = {
.set_rate = &omap2_clksel_set_rate,
};
+/* SCRM aux clk nodes */
+
+static const struct clksel auxclk_sel[] = {
+ { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+ { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+ { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk0_ck = {
+ .name = "auxclk0_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK0,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK0,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk1_ck = {
+ .name = "auxclk1_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK1,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK1,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk2_ck = {
+ .name = "auxclk2_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK2,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK2,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+static struct clk auxclk3_ck = {
+ .name = "auxclk3_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK3,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK3,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk4_ck = {
+ .name = "auxclk4_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK4,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK4,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk5_ck = {
+ .name = "auxclk5_ck",
+ .parent = &sys_clkin_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_omap2_dflt,
+ .clksel = auxclk_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK5,
+ .clksel_mask = OMAP4_SRCSELECT_MASK,
+ .recalc = &omap2_clksel_recalc,
+ .enable_reg = OMAP4_SCRM_AUXCLK5,
+ .enable_bit = OMAP4_ENABLE_SHIFT,
+};
+
+static const struct clksel auxclkreq_sel[] = {
+ { .parent = &auxclk0_ck, .rates = div_1_0_rates },
+ { .parent = &auxclk1_ck, .rates = div_1_1_rates },
+ { .parent = &auxclk2_ck, .rates = div_1_2_rates },
+ { .parent = &auxclk3_ck, .rates = div_1_3_rates },
+ { .parent = &auxclk4_ck, .rates = div_1_4_rates },
+ { .parent = &auxclk5_ck, .rates = div_1_5_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclkreq0_ck = {
+ .name = "auxclkreq0_ck",
+ .parent = &auxclk0_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq1_ck = {
+ .name = "auxclkreq1_ck",
+ .parent = &auxclk1_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq2_ck = {
+ .name = "auxclkreq2_ck",
+ .parent = &auxclk2_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq3_ck = {
+ .name = "auxclkreq3_ck",
+ .parent = &auxclk3_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq4_ck = {
+ .name = "auxclkreq4_ck",
+ .parent = &auxclk4_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq5_ck = {
+ .name = "auxclkreq5_ck",
+ .parent = &auxclk5_ck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .clksel = auxclkreq_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
+ .clksel_mask = OMAP4_MAPPING_MASK,
+ .recalc = &omap2_clksel_recalc,
+};
+
/*
* clkdev
*/
@@ -3083,6 +3246,18 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
+ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
+ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
+ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
+ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
+ CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
+ CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
+ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
+ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
+ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
+ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
+ CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
+ CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 07/12] OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocks
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (5 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 06/12] OMAP4: clock data: Add SCRM auxiliary clock nodes Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 08/12] OMAP2xxx clock: fix dss2_fck recalc to use clksel Paul Walmsley
` (6 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Rajendra Nayak <rnayak@ti.com>
The CORE and PER M3 post dividers are different from the rest of the
DPLL post dividers as in they go to SCRM, and are used
there to export clocks for instance used by external sensor.
There is no automatic HW dependency in PRCM to manage them. Hence these
two clocks (dpll post dividers) should be managed by SW and explicitly
enabled/disabled.
Add control in clock framework to handle that.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock44xx_data.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 80a1898..4c77613 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -610,7 +610,9 @@ static struct clk dpll_core_m3x2_ck = {
.clksel = dpll_core_m6x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- .ops = &clkops_null,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
@@ -869,7 +871,9 @@ static struct clk dpll_per_m3x2_ck = {
.clksel = dpll_per_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
- .ops = &clkops_null,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 08/12] OMAP2xxx clock: fix dss2_fck recalc to use clksel
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (6 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 07/12] OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocks Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 09/12] OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu Paul Walmsley
` (5 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
dss2_fck is a clksel clock, and therefore its rate should be recalculated
with the clksel mechanism. This was working in early 2009, but was one of
the casualties of the big OMAP clock merge between 2.6.29 and 2.6.30.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock2420_data.c | 2 +-
arch/arm/mach-omap2/clock2430_data.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 831e25c..7cfa186 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -812,7 +812,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
.clksel = dss2_fck_clksel,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
};
static struct clk dss_54m_fck = { /* Alt clk used in power management */
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index a9c60b7..3bd437a 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -800,7 +800,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
.clksel = dss2_fck_clksel,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
};
static struct clk dss_54m_fck = { /* Alt clk used in power management */
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 09/12] OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (7 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 08/12] OMAP2xxx clock: fix dss2_fck recalc to use clksel Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 10/12] OMAP3: clock: fix incorrect rate display when switching MPU rate at boot Paul Walmsley
` (4 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
Clarify the usage of the struct omap_clk.cpu flags (e.g., CK_*) to use
bits only for individual SoC variants (e.g., CK_3430ES1, CK_3505,
etc.). Superset flags, such as CK_3XXX or CK_AM35XX, are now defined
as disjunctions of individual SoC variant flags. This simplifies the
definition and use of these flags. struct omap_clk record definitions
can now simply specify the bitmask of actual SoCs that the records are
valid for. The clock init code can simply set a single CPU type mask
bit for the SoC that is currently in use, and test against that,
rather than needing to set some combination of flags.
Similarly, clarify the use of struct clksel_rate.flags. The bit
allocated for RATE_IN_3XXX has been reassigned, and RATE_IN_3XXX has
been defined as a disjunction of the 34xx and 36xx rate flags. The
advantages are the same as the above.
Clarify the usage of struct omap_clk.cpu flags such as CK_34XX to only
apply to the SoCs that they name, e.g., OMAP34xx chips. The previous
practice caused significantly different SoCs, such as OMAP36xx, to be
included in CK_34XX. In my opinion, this is much more intuitive.
Similarly, clarify the use of struct clksel_rate.flags, such that
RATE_IN_3430ES2PLUS now only applies to 34xx chips with ES level >= 2
- it does not apply to OMAP36xx.
...
At some point, it probably makes sense to collapse the CK_* and
RATE_IN_* flags together into a single bitfield, and possibly use the
existing CHIP_IS_OMAP* flags for platform detection.
...
This all seems to work fine on OMAP34xx and OMAP36xx Beagle. Not sure
if it works on Sitara or the TI816X, unfortunately I don't have any
here to test with.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock3xxx_data.c | 216 ++++++++++++-------------
arch/arm/plat-omap/include/plat/clkdev_omap.h | 20 +-
arch/arm/plat-omap/include/plat/clock.h | 11 +
3 files changed, 125 insertions(+), 122 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 94cbae3..84e43d3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
};
static const struct clksel_rate osc_sys_16_8m_rates[] = {
- { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
+ { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
{ .div = 0 }
};
@@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = {
static const struct clksel_rate div31_dpll3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
- { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
- { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
- { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
- { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
- { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
- { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
- { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
- { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
- { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
- { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
- { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
- { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
- { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
- { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
- { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
- { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
- { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
- { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
- { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
- { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
- { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
- { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
- { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
- { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
- { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
- { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
- { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
- { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
- { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
+ { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
{ .div = 0 },
};
@@ -3203,7 +3203,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
- CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
@@ -3220,8 +3220,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
- CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
- CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
+ CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
+ CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
CLK(NULL, "core_ck", &core_ck, CK_3XXX),
CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
@@ -3250,8 +3250,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
- CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
@@ -3259,8 +3259,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
- CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
- CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
+ CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
@@ -3269,24 +3269,24 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
- CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
- CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
- CLK(NULL, "modem_fck", &modem_fck, CK_343X),
- CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
- CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
+ CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
+ CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
- CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
- CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
+ CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
- CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
@@ -3304,27 +3304,27 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
- CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
+ CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
- CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
+ CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
- CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
+ CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
- CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
- CLK(NULL, "pka_ick", &pka_ick, CK_343X),
+ CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
- CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
- CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "icr_ick", &icr_ick, CK_343X),
- CLK("omap-aes", "ick", &aes2_ick, CK_343X),
- CLK("omap-sham", "ick", &sha12_ick, CK_343X),
- CLK(NULL, "des2_ick", &des2_ick, CK_343X),
+ CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
+ CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
+ CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
- CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
@@ -3340,40 +3340,40 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
- CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
- CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
- CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
+ CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
- CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
- CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
- CLK("omap_rng", "ick", &rng_ick, CK_343X),
- CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
- CLK(NULL, "des1_ick", &des1_ick, CK_343X),
+ CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
+ CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
+ CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
+ CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
- CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
- CLK(NULL, "cam_ick", &cam_ick, CK_343X),
- CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
- CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
- CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
- CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
- CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
- CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
+ CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
+ CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
+ CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
- CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
- CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
+ CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
@@ -3431,9 +3431,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
- CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
- CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
- CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
+ CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
+ CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
+ CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
@@ -3454,38 +3454,37 @@ static struct omap_clk omap3xxx_clks[] = {
int __init omap3xxx_clk_init(void)
{
struct omap_clk *c;
- u32 cpu_clkflg = CK_3XXX;
+ u32 cpu_clkflg = 0;
if (cpu_is_omap3517()) {
- cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
- cpu_clkflg |= CK_3517;
+ cpu_mask = RATE_IN_34XX;
+ cpu_clkflg = CK_3517;
} else if (cpu_is_omap3505()) {
- cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
- cpu_clkflg |= CK_3505;
+ cpu_mask = RATE_IN_34XX;
+ cpu_clkflg = CK_3505;
+ } else if (cpu_is_omap3630()) {
+ cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+ cpu_clkflg = CK_36XX;
} else if (cpu_is_omap34xx()) {
- cpu_mask = RATE_IN_3XXX;
- cpu_clkflg |= CK_343X;
-
- /*
- * Update this if there are further clock changes between ES2
- * and production parts
- */
if (omap_rev() == OMAP3430_REV_ES1_0) {
- /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
- cpu_clkflg |= CK_3430ES1;
+ cpu_mask = RATE_IN_3430ES1;
+ cpu_clkflg = CK_3430ES1;
} else {
- cpu_mask |= RATE_IN_3430ES2PLUS;
- cpu_clkflg |= CK_3430ES2;
+ /*
+ * Assume that anything that we haven't matched yet
+ * has 3430ES2-type clocks.
+ */
+ cpu_mask = RATE_IN_3430ES2PLUS;
+ cpu_clkflg = CK_3430ES2PLUS;
}
+ } else {
+ WARN(1, "clock: could not identify OMAP3 variant\n");
}
if (omap3_has_192mhz_clk())
omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
if (cpu_is_omap3630()) {
- cpu_mask |= RATE_IN_36XX;
- cpu_clkflg |= CK_36XX;
-
/*
* XXX This type of dynamic rewriting of the clock tree is
* deprecated and should be revised soon.
@@ -3532,10 +3531,9 @@ int __init omap3xxx_clk_init(void)
recalculate_root_clocks();
- printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
- (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+ pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+ (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
/*
* Only enable those clocks we will need, let the drivers
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index bb937f3..b19774c 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -31,18 +31,18 @@ struct omap_clk {
#define CK_1510 (1 << 2)
#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
#define CK_242X (1 << 4)
-#define CK_243X (1 << 5)
-#define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/
-#define CK_343X (1 << 7) /* OMAP34xx common clocks */
-#define CK_3430ES1 (1 << 8) /* 34xxES1 only */
-#define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505 (1 << 10)
-#define CK_3517 (1 << 11)
-#define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */
-#define CK_443X (1 << 13)
+#define CK_243X (1 << 5) /* 243x, 253x */
+#define CK_3430ES1 (1 << 6) /* 34xxES1 only */
+#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3505 (1 << 8)
+#define CK_3517 (1 << 9)
+#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
+#define CK_443X (1 << 11)
-#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
+#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
+#define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */
+#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index fef4696..6e22315 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -49,13 +49,18 @@ struct clkops {
/* struct clksel_rate.flags possibilities */
#define RATE_IN_242X (1 << 0)
#define RATE_IN_243X (1 << 1)
-#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */
-#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */
+#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
+#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
#define RATE_IN_36XX (1 << 4)
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
-#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX)
+#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
+
+/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
+
/**
* struct clksel_rate - register bitfield values corresponding to clk divisors
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 10/12] OMAP3: clock: fix incorrect rate display when switching MPU rate at boot
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (8 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 09/12] OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 11/12] OMAP2/3: SRAM: add comment about crashes during a TLB miss Paul Walmsley
` (3 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
The OMAP3 clock code contains some legacy code to allow the MPU rate
to be specified as a kernel command line parameter. If the 'mpurate'
parameter is specified, the kernel will attempt to switch the MPU rate
to this rate during boot. As part of this process, a short message
"Switched to new clocking rate" is generated -- and in this message,
the "Core" clock rate and "MPU" clock rate are transposed.
This patch ensures that the clock rates are displayed in the correct
order.
Thanks to Bruno Guerin <br_guerin@free.fr> for reporting this bug and
proposing a fix. Thanks to Richard Woodruff <r-woodruff2@ti.com> for
reviewing the problem and passing the report on.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Bruno Guerin <br.guerin@free.fr>
Cc: Richard Woodruff <r-woodruff2@ti.com>
---
arch/arm/mach-omap2/clock3xxx.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index a447c4d..90b9477 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -94,7 +94,7 @@ static int __init omap3xxx_clk_arch_init(void)
ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
if (!ret)
- omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck");
+ omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
return ret;
}
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 11/12] OMAP2/3: SRAM: add comment about crashes during a TLB miss
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (9 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 10/12] OMAP3: clock: fix incorrect rate display when switching MPU rate at boot Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:34 ` [PATCH 12/12] OMAP1: clock_data: use runtime cpu / machine checks Paul Walmsley
` (2 subsequent siblings)
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
Some users were observing crashes during the execution of CORE DVFS
code from OCM RAM -- a locally-modified copy of the linux-omap code.
Richard Woodruff tracked this down to a DTLB miss which had been
inadvertently and intermittently caused by the local modifications.
(The TLB miss caused the ARM MMU to attempt to walk the page tables
stored in SDRAM, which was not possible since SDRAM is off-line for a
portion of the CORE DVFS OCM RAM code.)
Add a note to the OMAP2 & OMAP3 CORE DVFS SRAM code to warn others that
changes may result in crashes here if they are not carefully tested.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/sram242x.S | 6 ++++++
arch/arm/mach-omap2/sram243x.S | 6 ++++++
arch/arm/mach-omap2/sram34xx.S | 6 ++++++
3 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 92e6e1a..6d88cee 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -21,6 +21,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible. Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index ab49736..2f104a6 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -21,6 +21,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible. Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 3637274..43f67f5 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -104,6 +104,12 @@
* touching the SDRAM. Until that time, users who know that their use case
* can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
* option.
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible. Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 12/12] OMAP1: clock_data: use runtime cpu / machine checks
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (10 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 11/12] OMAP2/3: SRAM: add comment about crashes during a TLB miss Paul Walmsley
@ 2010-12-14 6:34 ` Paul Walmsley
2010-12-14 6:49 ` [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Santosh Shilimkar
2010-12-14 20:05 ` Kevin Hilman
13 siblings, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Otherwise multi-omap1 configurations may set wrong clock speed.
Created and tested against l-o master on Amstrad Delta.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap1/clock_data.c | 17 ++++++++---------
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 423d21d..c7c2a52 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -823,12 +823,10 @@ int __init omap1_clk_init(void)
crystal_type = info->system_clock_type;
}
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
- ck_ref.rate = 13000000;
-#elif defined(CONFIG_ARCH_OMAP16XX)
- if (crystal_type == 2)
+ if (cpu_is_omap7xx())
+ ck_ref.rate = 13000000;
+ if (cpu_is_omap16xx() && crystal_type == 2)
ck_ref.rate = 19200000;
-#endif
pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
"0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
@@ -883,10 +881,11 @@ int __init omap1_clk_init(void)
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
- /* Select slicer output as OMAP input clock */
- omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
-#endif
+ if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
+ /* Select slicer output as OMAP input clock */
+ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
+ OMAP7XX_PCC_UPLD_CTRL);
+ }
/* Amstrad Delta wants BCLK high when inactive */
if (machine_is_ams_delta())
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (11 preceding siblings ...)
2010-12-14 6:34 ` [PATCH 12/12] OMAP1: clock_data: use runtime cpu / machine checks Paul Walmsley
@ 2010-12-14 6:49 ` Santosh Shilimkar
2010-12-14 6:53 ` Paul Walmsley
2010-12-14 6:53 ` Santosh Shilimkar
2010-12-14 20:05 ` Kevin Hilman
13 siblings, 2 replies; 24+ messages in thread
From: Santosh Shilimkar @ 2010-12-14 6:49 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Paul Walmsley
> Sent: Tuesday, December 14, 2010 12:05 PM
> To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
>
I guess you wanted to say "SCRM" instead of SRAM in subject line
> This clock/SRAM patch series, based on v2.6.37-rc5:
>
> - fixes some problems and missing data with OMAP4 clocks,
>
> - adds SCRM IP block data (part of the OMAP4 PRCM collection of
modules),
>
> - cleans up the way that OMAP3 clock data CK_* and RATE_IN_* flags are
> used,
>
> - adds some comments to the SRAM code,
>
> - prepares part of the OMAP1 clock code for a combined OMAP1 defconfig
> (although more work is left to be done before a combined OMAP1
> defconfig is safe, from a clock framework perspective),
>
> - and fixes a few minor bugs in the OMAP2/3 clock code.
>
>
> Boot-tested on OSK 5912, N800, OMAP35xx Beagle, and OMAP37xx Beagle-XM.
>
> This series is also available from git://git.pwsan.com/linux-2.6
> branch 'clk_a_2.6.38'.
>
>
> - Paul
>
> ---
>
> clk_a_2.6.38
> text data bss dec hex filename
> 5733349 471616 5608768 11813733 b44365 vmlinux.orig
> 5734273 473728 5608768 11816769 b44f41
> vmlinux.patched
>
>
> Benoit Cousson (3):
> OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk
> OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck
> OMAP4: PRCM: Add SCRM header file
>
> Janusz Krzysztofik (1):
> OMAP1: clock_data: use runtime cpu / machine checks
>
> Jonathan Bergsagel (1):
> OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ck
>
> Paul Walmsley (4):
> OMAP2xxx clock: fix dss2_fck recalc to use clksel
> OMAP3: clock: clarify usage of struct clksel_rate.flags and struct
> omap_clk.cpu
> OMAP3: clock: fix incorrect rate display when switching MPU rate
at
> boot
> OMAP2/3: SRAM: add comment about crashes during a TLB miss
>
> Rajendra Nayak (2):
> OMAP4: clock data: Add SCRM auxiliary clock nodes
> OMAP4: clock data: Export control to enable/disable CORE/PER M3
> clocks
>
> Thara Gopinath (1):
> OMAP4: clock data: Add missing DPLL x2 clock nodes
>
>
> arch/arm/mach-omap1/clock_data.c | 17 -
> arch/arm/mach-omap2/clock2420_data.c | 2
> arch/arm/mach-omap2/clock2430_data.c | 2
> arch/arm/mach-omap2/clock3xxx.c | 2
> arch/arm/mach-omap2/clock3xxx_data.c | 218 ++++-----
> arch/arm/mach-omap2/clock44xx_data.c | 620
++++++++++++++++++--
> -----
> arch/arm/mach-omap2/scrm44xx.h | 176 +++++++
> arch/arm/mach-omap2/sram242x.S | 6
> arch/arm/mach-omap2/sram243x.S | 6
> arch/arm/mach-omap2/sram34xx.S | 6
> arch/arm/plat-omap/include/plat/clkdev_omap.h | 20 -
> arch/arm/plat-omap/include/plat/clock.h | 11
> 12 files changed, 772 insertions(+), 314 deletions(-)
> create mode 100644 arch/arm/mach-omap2/scrm44xx.h
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
2010-12-14 6:49 ` [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Santosh Shilimkar
@ 2010-12-14 6:53 ` Paul Walmsley
2010-12-14 6:53 ` Santosh Shilimkar
1 sibling, 0 replies; 24+ messages in thread
From: Paul Walmsley @ 2010-12-14 6:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 14 Dec 2010, Santosh Shilimkar wrote:
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Paul Walmsley
> > Sent: Tuesday, December 14, 2010 12:05 PM
> > To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> > Subject: [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
> >
> I guess you wanted to say "SCRM" instead of SRAM in subject line
SRAM was, in fact, intentional. But maybe, if the series is reposted, I
might add SCRM also.
- Paul
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
2010-12-14 6:49 ` [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Santosh Shilimkar
2010-12-14 6:53 ` Paul Walmsley
@ 2010-12-14 6:53 ` Santosh Shilimkar
1 sibling, 0 replies; 24+ messages in thread
From: Santosh Shilimkar @ 2010-12-14 6:53 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Tuesday, December 14, 2010 12:19 PM
> To: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: RE: [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part
one
>
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Paul Walmsley
> > Sent: Tuesday, December 14, 2010 12:05 PM
> > To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> > Subject: [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
> >
> I guess you wanted to say "SCRM" instead of SRAM in subject line
>
Please ignore my comment Paul. The series does have a SRAM fix.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one
2010-12-14 6:34 [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Paul Walmsley
` (12 preceding siblings ...)
2010-12-14 6:49 ` [PATCH 00/12] OMAP: clock/SRAM: patches for 2.6.38, part one Santosh Shilimkar
@ 2010-12-14 20:05 ` Kevin Hilman
13 siblings, 0 replies; 24+ messages in thread
From: Kevin Hilman @ 2010-12-14 20:05 UTC (permalink / raw)
To: linux-arm-kernel
Paul Walmsley <paul@pwsan.com> writes:
> This clock/SRAM patch series, based on v2.6.37-rc5:
>
> - fixes some problems and missing data with OMAP4 clocks,
>
> - adds SCRM IP block data (part of the OMAP4 PRCM collection of modules),
>
> - cleans up the way that OMAP3 clock data CK_* and RATE_IN_* flags are
> used,
>
> - adds some comments to the SRAM code,
>
> - prepares part of the OMAP1 clock code for a combined OMAP1 defconfig
> (although more work is left to be done before a combined OMAP1
> defconfig is safe, from a clock framework perspective),
>
> - and fixes a few minor bugs in the OMAP2/3 clock code.
>
>
> Boot-tested on OSK 5912, N800, OMAP35xx Beagle, and OMAP37xx Beagle-XM.
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
Also boot tesed on omap4/panda and PM tested on 3430/n900 with retention
idle & suspend and off idle & suspend.
Kevin
> This series is also available from git://git.pwsan.com/linux-2.6
> branch 'clk_a_2.6.38'.
>
>
> - Paul
>
> ---
>
> clk_a_2.6.38
> text data bss dec hex filename
> 5733349 471616 5608768 11813733 b44365 vmlinux.orig
> 5734273 473728 5608768 11816769 b44f41 vmlinux.patched
>
>
> Benoit Cousson (3):
> OMAP4: clock data: Add control for pad_clks_ck and slimbus_clk
> OMAP3: clock data: Add "wkup_clkdm" in sr1_fck and sr2_fck
> OMAP4: PRCM: Add SCRM header file
>
> Janusz Krzysztofik (1):
> OMAP1: clock_data: use runtime cpu / machine checks
>
> Jonathan Bergsagel (1):
> OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ck
>
> Paul Walmsley (4):
> OMAP2xxx clock: fix dss2_fck recalc to use clksel
> OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu
> OMAP3: clock: fix incorrect rate display when switching MPU rate at boot
> OMAP2/3: SRAM: add comment about crashes during a TLB miss
>
> Rajendra Nayak (2):
> OMAP4: clock data: Add SCRM auxiliary clock nodes
> OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocks
>
> Thara Gopinath (1):
> OMAP4: clock data: Add missing DPLL x2 clock nodes
>
>
> arch/arm/mach-omap1/clock_data.c | 17 -
> arch/arm/mach-omap2/clock2420_data.c | 2
> arch/arm/mach-omap2/clock2430_data.c | 2
> arch/arm/mach-omap2/clock3xxx.c | 2
> arch/arm/mach-omap2/clock3xxx_data.c | 218 ++++-----
> arch/arm/mach-omap2/clock44xx_data.c | 620 ++++++++++++++++++-------
> arch/arm/mach-omap2/scrm44xx.h | 176 +++++++
> arch/arm/mach-omap2/sram242x.S | 6
> arch/arm/mach-omap2/sram243x.S | 6
> arch/arm/mach-omap2/sram34xx.S | 6
> arch/arm/plat-omap/include/plat/clkdev_omap.h | 20 -
> arch/arm/plat-omap/include/plat/clock.h | 11
> 12 files changed, 772 insertions(+), 314 deletions(-)
> create mode 100644 arch/arm/mach-omap2/scrm44xx.h
>
> --
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^ permalink raw reply [flat|nested] 24+ messages in thread