From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2182CC433DB for ; Thu, 7 Jan 2021 11:08:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B064723125 for ; Thu, 7 Jan 2021 11:08:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B064723125 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=misterjones.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CR99/SDniH87RbSwmPxM3rxauKoB7fFrcDKcSzeTPoo=; b=QSxUutc7JKFrTkZRDP0E3OSH8 U/zNOYamZKfZjbZEdd3JGgrC7J6PPmcDWsWQyYImJfGICN8n1D0v5J5708NHj9A/+5CoA9va0tiFT 5lrwkxHM8irtcf2Q3B8HJ0corLczXXugpWAoSQ1XgAfvkLWiTlxpWjODbcV5fMaul36yXmpJZDVDp L1hFNkTFxxo8ZpfP2VH7jv7w0xvZVOpy22JwfW5yfs9toqhXCJBWgGAFJJKQ0zPa9CMHZ0w8U/L1R nraZKQtC9Iw7iY6A4EFfgTvOpiAwJ8oWpmV2zgJLvRLK3uCAw0taoXReE4Lsz3IV0508462ypaRGG e3YfLe+Dg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxT71-0008Ls-9x; Thu, 07 Jan 2021 11:05:51 +0000 Received: from disco-boy.misterjones.org ([51.254.78.96]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxT6y-0008Ka-9T for linux-arm-kernel@lists.infradead.org; Thu, 07 Jan 2021 11:05:49 +0000 Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kxT6Q-005orL-Rd; Thu, 07 Jan 2021 11:05:14 +0000 MIME-Version: 1.0 Date: Thu, 07 Jan 2021 11:05:14 +0000 From: Marc Zyngier To: Sascha Hauer Subject: Re: [PATCH 1/1] drivers/edac: Add L1 and L2 error detection for A53 and A57 In-Reply-To: <20210107103819.13552-2-s.hauer@pengutronix.de> References: <20210107103819.13552-1-s.hauer@pengutronix.de> <20210107103819.13552-2-s.hauer@pengutronix.de> User-Agent: Roundcube Webmail/1.4.9 Message-ID: <87bfbf704e4c2f13b30fe7055b8dec40@misterjones.org> X-Sender: maz@misterjones.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: s.hauer@pengutronix.de, linux-edac@vger.kernel.org, tony.luck@intel.com, robh+dt@kernel.org, rrichter@marvell.com, james.morse@arm.com, kernel@pengutronix.de, bp@alien8.de, york.sun@nxp.com, mchehab@kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@misterjones.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210107_060548_340567_58E320A7 X-CRM114-Status: GOOD ( 23.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tony Luck , Rob Herring , Robert Richter , James Morse , kernel@pengutronix.de, Borislav Petkov , York Sun , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-01-07 10:38, Sascha Hauer wrote: > The Cortex A53 and A57 cores have error detection capabilities for the > L1/L2 Caches, this patch adds a driver for them. > > Unfortunately there is no robust way to inject errors into the caches, > so this driver doesn't contain any code to actually test it. It has > been tested though with code taken from an older version of this driver > found here: https://lkml.org/lkml/2018/3/14/1203. For reasons stated > in this thread the error injection code is not suitable for mainline, > so it is removed from the driver. > > Signed-off-by: Sascha Hauer > --- > drivers/edac/Kconfig | 6 + > drivers/edac/Makefile | 1 + > drivers/edac/cortex_arm64_l1_l2.c | 218 ++++++++++++++++++++++++++++++ > 3 files changed, 225 insertions(+) > create mode 100644 drivers/edac/cortex_arm64_l1_l2.c > > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig > index 81c42664f21b..116ad56534a4 100644 > --- a/drivers/edac/Kconfig > +++ b/drivers/edac/Kconfig > @@ -539,4 +539,10 @@ config EDAC_DMC520 > Support for error detection and correction on the > SoCs with ARM DMC-520 DRAM controller. > > +config EDAC_CORTEX_ARM64_L1_L2 > + tristate "ARM Cortex A57/A53" > + depends on ARM64 > + help > + Support for L1/L2 cache error detection on ARM Cortex A57 and A53. > + > endif # EDAC > diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile > index 464d3d8d850a..a324fbc1693e 100644 > --- a/drivers/edac/Makefile > +++ b/drivers/edac/Makefile > @@ -89,3 +89,4 @@ obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o > obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o > obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o > obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o > +obj-$(CONFIG_EDAC_CORTEX_ARM64_L1_L2) += cortex_arm64_l1_l2.o > diff --git a/drivers/edac/cortex_arm64_l1_l2.c > b/drivers/edac/cortex_arm64_l1_l2.c > new file mode 100644 > index 000000000000..3b1e2f3ccab6 > --- /dev/null > +++ b/drivers/edac/cortex_arm64_l1_l2.c > @@ -0,0 +1,218 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Cortex A57 and A53 EDAC L1 and L2 cache error detection > + * > + * Copyright (c) 2020 Pengutronix, Sascha Hauer > > + * > + * Based on Code from: > + * Copyright (c) 2018, NXP Semiconductor > + * Author: York Sun > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#include "edac_module.h" > + > +#define DRVNAME "cortex-arm64-edac" > + > +#define CPUMERRSR_EL1_RAMID GENMASK(30, 24) > + > +#define CPUMERRSR_EL1_VALID BIT(31) > +#define CPUMERRSR_EL1_FATAL BIT(63) > + > +#define L1_I_TAG_RAM 0x00 > +#define L1_I_DATA_RAM 0x01 > +#define L1_D_TAG_RAM 0x08 > +#define L1_D_DATA_RAM 0x09 > +#define L1_D_DIRTY_RAM 0x14 > +#define TLB_RAM 0x18 > + > +#define L2MERRSR_EL1_VALID BIT(31) > +#define L2MERRSR_EL1_FATAL BIT(63) > + > +struct merrsr { > + u64 cpumerr; > + u64 l2merr; > +}; > + > +#define MESSAGE_SIZE 64 > + > +#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2) > +#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3) Oh, IMPDEF registers... This means that a kernel with this driver running in a virtualized environment is likely to just take an UNDEF and die. Not great. Also, how does it work if EL3 implements the same functionality? M. -- Who you jivin' with that Cosmik Debris? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel