Re: [PATCH v2 2/8] KVM: arm64: Handle negative S1 walk levels in VNCR TLB size evaluation

[Marc Zyngier <maz@kernel.org>]

On Fri, 07 Aug 2026 18:12:18 +0100,
"Lorenzo Stoakes (ARM)" <ljs@kernel.org> wrote:

[...]

> So actually if granularity is TLBI_TTL_TG_4K this will return SZ_1G and 0 in the
> other cases unless I'm getting something wrong here?
>
> This is really more a 'maybe worth mentioning in the commit log to be pedantic'
> kind of thing :)
> 
> IOW you could luck out before with SZ_1G for TLBI_TTL_TG_4K.

Yes, and that's what happens in most cases. But as Huynwoo Kim's
reports, 16k and 64k lead to something really bad. And even 4k works
by pure luck, so this is all fsck'd in my book.

> 
> >
> > Tidy-up pgshift_level_to_ttl() to handle these negative levels, and
> > ttl_to_size() to always return SZ_1G when no valid TTL is present.
> > This allows the removal of open-coded checks for similar situations.
> 
> I guess SZ_1G is a reasonable default here?

It is more than a reasonable default. It is the maximum block size
that can architecturally be mapped in the absence of FEAT_LPA*. In
this situation, 16k pages imply a 32M max block mapping, and 64k
implies 512M. 4K pages, by virtue of allowing a level-1 block mapping
result in a 1G size.

> 
> >
> > Note that the check for a negative value not explicitely checking for
> 
> NIT: explicitely -> explicitly
> 
> > S1_MMU_DISABLED is deliberate, so that actual negative levels introduced
> > with LVA2 and D128 can take the same path if we ever support them.
> >
> > Fixes: 7270cc9157f47 ("KVM: arm64: nv: Handle VNCR_EL2 invalidation from MMU notifiers")
> > Reported-by: Hyunwoo Kim <imv4bel@gmail.com>
> > Link: https://lore.kernel.org/r/ameGoxbn2wzBq2kL@v4bel
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > Cc: stable@vger.kernel.org
> > ---
> >  arch/arm64/kvm/nested.c | 26 +++++++++++++++++++-------
> >  1 file changed, 19 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> > index f3c75954cf36c..035cda256e2a5 100644
> > --- a/arch/arm64/kvm/nested.c
> > +++ b/arch/arm64/kvm/nested.c
> > @@ -505,7 +505,7 @@ int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa,
> >  	return ret;
> >  }
> >
> > -static unsigned int ttl_to_size(u8 ttl)
> > +static unsigned int __ttl_to_size(u8 ttl)
> >  {
> >  	int level = ttl & 3;
> >  	int gran = (ttl >> 2) & 3;
> > @@ -561,10 +561,22 @@ static unsigned int ttl_to_size(u8 ttl)
> >  	return max_size;
> >  }
> >
> > -static u8 pgshift_level_to_ttl(u16 shift, u8 level)
> > +static unsigned int ttl_to_size(u8 ttl)
> > +{
> > +	return __ttl_to_size(ttl) ?: SZ_1G;
> > +}
> 
> Might be worth a comment about the default?

It's the architecture. I'm trying hard not to make KVM a running
commentary of the ARM ARM ;-).

> 
> > +
> > +static u8 pgshift_level_to_ttl(u16 shift, s8 level)
> >  {
> >  	u8 ttl;
> >
> > +	/*
> > +	 * If we don't have a proper level, fallback to the maximum
> > +	 * size.
> > +	 */
> > +	if (level < 0)
> > +		return 0;
> > +
> >  	switch(shift) {
> >  	case 12:
> >  		ttl = TLBI_TTL_TG_4K;
> > @@ -675,7 +687,11 @@ unsigned long compute_tlb_inval_range(struct kvm_s2_mmu *mmu, u64 val)
> >  		ttl = get_guest_mapping_ttl(mmu, addr);
> >  	}
> >
> > -	max_size = ttl_to_size(ttl);
> > +	/*
> > +	 * Don't use the default 1GB fallback, as we can adapt to the
> > +	 * max mapping size we allow at S2.
> > +	 */
> 
> Being a bit pedantic here but I wonder if simply just to say 'Adapt to the max
> mapping size allowed at S2' as the fallback is inferred?

Sure.

Thanks,

	M.

-- 
Jazz isn't dead. It just smells funny.