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Thu, 01 Jun 2023 13:48:43 +0100 Date: Thu, 01 Jun 2023 13:48:42 +0100 Message-ID: <87bkhzpcut.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Zenghui Yu , Quentin Perret , Will Deacon , Fuad Tabba Subject: Re: [PATCH v2 05/17] arm64: Don't enable VHE for the kernel if OVERRIDE_HVHE is set In-Reply-To: References: <20230526143348.4072074-1-maz@kernel.org> <20230526143348.4072074-6-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 109.23.4.90 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, qperret@google.com, will@kernel.org, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230601_054847_212728_9544A3C4 X-CRM114-Status: GOOD ( 30.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 01 Jun 2023 08:32:40 +0100, Oliver Upton wrote: > > On Fri, May 26, 2023 at 03:33:36PM +0100, Marc Zyngier wrote: > > If the OVERRIDE_HVHE SW override is set (as a precursor of > > the KVM_HVHE capability), do not enable VHE for the kernel > > and drop to EL1 as if VHE was either disabled or unavailable. > > > > Further changes will enable VHE at EL2 only, with the kernel > > still running at EL1. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kernel/hyp-stub.S | 10 +++++++++- > > 1 file changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S > > index 9439240c3fcf..5c71e1019545 100644 > > --- a/arch/arm64/kernel/hyp-stub.S > > +++ b/arch/arm64/kernel/hyp-stub.S > > @@ -82,7 +82,15 @@ SYM_CODE_START_LOCAL(__finalise_el2) > > tbnz x1, #0, 1f > > > > // Needs to be VHE capable, obviously > > - check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f x1 x2 > > + check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 0f 1f x1 x2 > > + > > +0: // Check whether we only want the hypervisor to run VHE, not the kernel > > + adr_l x1, arm64_sw_feature_override > > + ldr x2, [x1, FTR_OVR_VAL_OFFSET] > > + ldr x1, [x1, FTR_OVR_MASK_OFFSET] > > + and x2, x2, x1 > > nit: is applying the mask even necessary? I get it in the context of an > overlay on top of an ID register, but the software features are more of > a synthetic ID register in their own right. I guess I don't have a good reason just yet, but on the other hand it makes things predictable if the override code refuses the override for some reason other than not being VHE-capable (mask becomes 0 and val becomes 0xf). Overall, I feel that this code is too hard to follow to do anything different from the "standard" case. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel