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Tue, 10 Aug 2021 09:41:06 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mDOD6-003KNc-T1 for linux-arm-kernel@lists.infradead.org; Tue, 10 Aug 2021 09:38:14 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9818561078; Tue, 10 Aug 2021 09:38:12 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mDOD4-0041Tz-KE; Tue, 10 Aug 2021 10:38:10 +0100 Date: Tue, 10 Aug 2021 10:38:10 +0100 Message-ID: <87bl65bpx9.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Paolo Bonzini , Sean Christopherson , Peter Shier , Jim Mattson , David Matlack , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Andrew Jones , Will Deacon , Catalin Marinas Subject: Re: [PATCH v6 16/21] arm64: cpufeature: Enumerate support for Enhanced Counter Virtualization In-Reply-To: <20210804085819.846610-17-oupton@google.com> References: <20210804085819.846610-1-oupton@google.com> <20210804085819.846610-17-oupton@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@google.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, seanjc@google.com, pshier@google.com, jmattson@google.com, dmatlack@google.com, ricarkol@google.com, jingzhangos@google.com, rananta@google.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, drjones@redhat.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210810_023813_040573_AEAD28BC X-CRM114-Status: GOOD ( 21.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 04 Aug 2021 09:58:14 +0100, Oliver Upton wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2). > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/sysreg.h | 2 ++ > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 13 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 7b9c3acba684..4dfc44066dfb 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -847,6 +847,8 @@ > #define ID_AA64MMFR0_ASID_SHIFT 4 > #define ID_AA64MMFR0_PARANGE_SHIFT 0 > > +#define ID_AA64MMFR0_ECV_VIRT 0x1 > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 > #define ID_AA64MMFR0_TGRAN64_NI 0xf > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 0ead8bfedf20..94c349e179d3 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_ECV, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..d819ea614da5 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -3,6 +3,7 @@ > # Internal CPU capabilities constants, keep this list sorted > > BTI > +ECV > # Unreliable: use system_supports_32bit_el0() instead. > HAS_32BIT_EL0_DO_NOT_USE > HAS_32BIT_EL1 As discussed in another context, we probably want both ECV and ECV2 to distinguish the two feature sets that ECV has so far. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel