From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0658C2D0E4 for ; Thu, 19 Nov 2020 05:50:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2E22238E6 for ; Thu, 19 Nov 2020 05:50:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ieLRs+B3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2E22238E6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6BjNlJ4s9QRR4fPyiKDtAIK8RN0aF4SdbiAWwoMQJMg=; b=ieLRs+B3DLT7L50Tp8CpbUn0n dAt9JPz9EFfinBUikodFg0fUOJ3ttxbedOd2n1e1iTEmcupZKzhRwhjCAwziJSqQZKkP1Kf3Y0nhy k+ORL5g4xChtcS00/y/lBkyzUvBxVm73pLxYU1VUorW3KLl5C21j2ZxZzfkh7bmQ3arSZQOnDT9cI Vj/FsgotYJr6pnDJXqVDs8HexZfq09ENqJaL6ej4PZzhe6xidJ3IZQ851Evxt/nviPWLU2XKjD/uP n2LO+2WH1GoUvQUhETklltgx0ZG7C9d0s9HdCah++O9C4SUKjpfBvTlXSzUKMtBHLtYqxrxuj1j1c TZGZyeZ+w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfcpM-0005OE-GS; Thu, 19 Nov 2020 05:49:52 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfcpE-0005Nn-LT for linux-arm-kernel@lists.infradead.org; Thu, 19 Nov 2020 05:49:50 +0000 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 8193344064C; Thu, 19 Nov 2020 07:49:26 +0200 (IST) References: <20201118224632.GE1853236@lunn.ch> User-agent: mu4e 1.4.13; emacs 26.3 From: Baruch Siach To: Andrew Lunn Subject: Re: [PATCH 0/5] gpio: mvebu: Armada 8K/7K PWM support In-reply-to: <20201118224632.GE1853236@lunn.ch> Date: Thu, 19 Nov 2020 07:49:24 +0200 Message-ID: <87blft6gm3.fsf@tarshish> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_004946_421864_9726EDE6 X-CRM114-Status: GOOD ( 23.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, Sascha Hauer , Jason Cooper , linux-gpio@vger.kernel.org, Linus Walleij , Chris Packham , Bartosz Golaszewski , Thierry Reding , Thomas Petazzoni , Uwe =?utf-8?Q?Kleine-K?= =?utf-8?Q?=C3=B6nig?= , Ralph Sennhauser , Lee Jones , Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andrew, Thanks for your review comments. On Thu, Nov 19 2020, Andrew Lunn wrote: > On Wed, Nov 18, 2020 at 12:30:41PM +0200, Baruch Siach wrote: >> The gpio-mvebu driver supports the PWM functionality of the GPIO block for >> earlier Armada variants like XP, 370 and 38x. This series extends support to >> newer Armada variants that use CP11x and AP80x, like Armada 8K and 7K. >> >> This series adds adds the 'pwm-offset' property to DT binding. 'pwm-offset' > > One adds is enough. > >> points to the base of A/B counter registers that determine the PWM period and >> duty cycle. >> >> The existing PWM DT binding reflects an arbitrary decision to allocate the A >> counter to the first GPIO block, and B counter to the other one. > > It was not arbitrary. I decided on KISS. The few devices i've seen > using this have been for a single GPIO/PWN controlled fan. KISS was > sufficient for that, so why make it more complex? In saying "arbitrary" I don't mean to say it's not a good choice in the context of the Linux PWM and GPIO subsystems. But this choice is still arbitrary from hardware point of view. DT is meant to describe the hardware. I think that coding the A/B counters allocation choice in DT is not optimal in terms for hardware description. Both counters are usable for both GPIO blocks. I also don't see how this makes anything more complex. The driver code is already aware of this A/B allocation (GPIO_BLINK_CNT_SELECT_OFF). My suggestion is to keep this decision in the driver, and leave DT to describe the hardware. This costs us a single code line (patch #3): mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; Does that make sense? baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il - _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel