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boundary="===============2369783410744883040==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============2369783410744883040== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Hi, Manish Narani writes: >> -----Original Message----- >> From: Felipe Balbi >> Sent: Tuesday, September 1, 2020 5:45 PM >>=20 >> >> > + goto err; >> >> > + } >> >> > + >> >> > + ret =3D dwc3_xlnx_rst_assert(priv_data->apbrst); >> >> > + if (ret < 0) { >> >> > + dev_err(dev, "%s: %d: Failed to assert reset\n", >> >> > + __func__, __LINE__); >> >> >> >> dev_err(dev, "Failed to assert APB reset\n"); >> >> >> >> > + goto err; >> >> > + } >> >> > + >> >> > + ret =3D phy_init(priv_data->usb3_phy); >> >> >> >> dwc3 core should be handling this already >> > >> > The USB controller used in Xilinx ZynqMP platform uses xilinx GT phy >> > which has 4 GT lanes and can used by 4 peripherals at a time. >>=20 >> At the same time or are they mutually exclusive? > > The lanes are mutually exclusive. Thank you for confirming :-) > [...] >> >> > + if (ret < 0) { >> >> > + dev_err(dev, "%s: %d: Failed to release reset\n", >> >> > + __func__, __LINE__); >> >> > + goto err; >> >> > + } >> >> > + >> >> > + /* Set PIPE power present signal */ >> >> > + writel(PIPE_POWER_ON, priv_data->regs + PIPE_POWER_OFFSET); >> >> > + >> >> > + /* Clear PIPE CLK signal */ >> >> > + writel(PIPE_CLK_OFF, priv_data->regs + PIPE_CLK_OFFSET); >> >> >> >> shouldn't this be hidden under clk_enable()? >> > >> > Though its naming suggests something related to clock framework, it is >> > a register in the Xilinx USB controller space which configures the >> > PIPE clock coming from Serdes. >>=20 >> PIPE clock is a clock. It just so happens that the source is the PHY >> itself. > > This bit is used to choose between PIPE clock coming from SerDes > and the Suspend Clock. When the controller is out of reset, this bit > needs to be reset in order to make the USB controller work. This > register is added in Xilinx USB controller register space. I will > add more description about the same in v2. Aha! That clarifies. It's just a clock selection from clocks that are generated elsewhere :-) I guess a clk driver would be overkill, indeed. Thanks for explaining. Could you add some of this information to commit log, then? cheers =2D-=20 balbi --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQJFBAEBCAAvFiEElLzh7wn96CXwjh2IzL64meEamQYFAl9YreIRHGJhbGJpQGtl cm5lbC5vcmcACgkQzL64meEamQZ/zw/7Btf7KF38ujarqULDRAGPcndKWFLsg+zM mf6UkIlysLp3RK3ADxwyLi+9jwnezvSTQ7wHU1E3jF5aHsVpahXOtkkjS6ffYhyG LyOGMJNJ1/h4i+QyNs5mkfOTNSP02W0mfd2VrzWse9A1IMqJeoo0xVjrqyZixZEd 6FaO1mfIXfFFQnfS5q5hZo9GYk6HNM929VKs09bX2uJ8qsJqcI+i5SAdxbo+Zp4T 2PxrQtcQEYxjL2R39AbAy6U627ZfEtuHrIOtTV5czMqzPAIfi/88WnXvriT7oOcM GrvAz+ulf8uSMwNtVc3GUzkFgpppshjoB71WojNxlfbt/5UYLTLyFOfDfPf2i4gE Q6EKRU3NPJcnt/2letLFfhSow6qnLuCFYCfl6z+8lgbLHoThfmNtUrx4jlVrPFMJ Sz1bSR5NO82aNvbhOIXWGcyoaiZBpYPX0XVyW0wDEc+dnal4oUE12MxOVhzk6QVz FqBdmDKXx+jjwwKkWoBONLsTvjScG5PXPMTOMGFffVSnrJ6f8bo1QGuwL8H72uqj 4z44XEbYjiWGFYroG3VsoVJvf/vGjsfud0ZJLesKF37BeaU1jJkbYQQQjLM9WzXY IZ0Mg04mcVLl1vhCDK3KZH0B/8vMDiUgduLflBtuuxPqVU/wAr74jgLRJMDppBDH vE++F+UPao4= =+Qxk -----END PGP SIGNATURE----- --=-=-=-- --===============2369783410744883040== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============2369783410744883040==--