From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Marc Zyngier <maz@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@bootlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev
Subject: Re: [PATCH v3 10/10] irqchip/riscv-imsic: Use IRQCHIP_MOVE_DEFERRED flag for PCI devices
Date: Tue, 04 Feb 2025 16:20:28 +0100 [thread overview]
Message-ID: <87cyfxohxf.ffs@tglx> (raw)
In-Reply-To: <CAK9=C2VgOnSVBRPh+bJBQnGreVYcUh6HWVg1MEzDtfYsuT0s-g@mail.gmail.com>
On Tue, Feb 04 2025 at 20:19, Anup Patel wrote:
> On Tue, Feb 4, 2025 at 2:26 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>> The same could be achieved by executing that intermediate transition on
>> CPU0 with interrupts disabled by affining the calling context (thread)
>> to CPU0 or by issuing an IPI on CPU0 and doing it in that context. I
>> looked into that, but that has it's own pile of issues. So at the end
>> moving it in the context of the interrupt on the original CPU/vector
>> turned out to be the simplest way to achieve it.
>
> I got confused because IRQCHIP_MOVE_DEFERRED updates affinity
> with the interrupt masked which I interpreted as masked at the device
> level. Also, PCI MSI mask/unmask is an optional feature of PCI devices
> which I totally missed.
That's the problem this actually handles. If PCI mask/unmask would be
mandatory the problem would not exist in the first place :)
prev parent reply other threads:[~2025-02-04 15:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-04 7:53 [PATCH v3 00/10] RISC-V IMSIC driver improvements Anup Patel
2025-02-04 7:53 ` [PATCH v3 01/10] irqchip/riscv-imsic: Handle non-atomic MSI updates for device Anup Patel
2025-02-04 13:08 ` Thomas Gleixner
2025-02-04 14:51 ` Anup Patel
2025-02-04 7:53 ` [PATCH v3 02/10] irqchip/irq-msi-lib: Optionally set default irq_eoi/irq_ack Anup Patel
2025-02-04 7:53 ` [PATCH v3 03/10] irqchip/riscv-imsic: Set irq_set_affinity for IMSIC base Anup Patel
2025-02-04 7:53 ` [PATCH v3 04/10] irqchip/riscv-imsic: Move to common MSI lib Anup Patel
2025-02-04 7:54 ` [PATCH v3 05/10] genirq: Introduce common irq_force_complete_move() implementation Anup Patel
2025-02-04 7:54 ` [PATCH v3 06/10] RISC-V: Enable GENERIC_PENDING_IRQ and GENERIC_PENDING_IRQ_CHIPFLAGS Anup Patel
2025-02-04 7:54 ` [PATCH v3 07/10] irqchip/riscv-imsic: Separate next and previous pointers in IMSIC vector Anup Patel
2025-02-04 7:54 ` [PATCH v3 08/10] irqchip/riscv-imsic: Implement irq_force_complete_move() for IMSIC Anup Patel
2025-02-04 7:54 ` [PATCH v3 09/10] irqchip/riscv-imsic: Replace hwirq with irq in the IMSIC vector Anup Patel
2025-02-04 7:54 ` [PATCH v3 10/10] irqchip/riscv-imsic: Use IRQCHIP_MOVE_DEFERRED flag for PCI devices Anup Patel
2025-02-04 8:56 ` Thomas Gleixner
2025-02-04 14:49 ` Anup Patel
2025-02-04 15:20 ` Thomas Gleixner [this message]
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